KR20120101136A - 반도체 다이 뒤틀림을 제어하기 위한 장치 및 방법 - Google Patents

반도체 다이 뒤틀림을 제어하기 위한 장치 및 방법 Download PDF

Info

Publication number
KR20120101136A
KR20120101136A KR1020127018759A KR20127018759A KR20120101136A KR 20120101136 A KR20120101136 A KR 20120101136A KR 1020127018759 A KR1020127018759 A KR 1020127018759A KR 20127018759 A KR20127018759 A KR 20127018759A KR 20120101136 A KR20120101136 A KR 20120101136A
Authority
KR
South Korea
Prior art keywords
semiconductor die
vias
silicon
die
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020127018759A
Other languages
English (en)
Korean (ko)
Inventor
쉐 배이
울미 레이
Original Assignee
콸콤 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 콸콤 인코포레이티드 filed Critical 콸콤 인코포레이티드
Publication of KR20120101136A publication Critical patent/KR20120101136A/ko
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020127018759A 2009-12-17 2010-12-17 반도체 다이 뒤틀림을 제어하기 위한 장치 및 방법 Abandoned KR20120101136A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/640,111 2009-12-17
US12/640,111 US8710629B2 (en) 2009-12-17 2009-12-17 Apparatus and method for controlling semiconductor die warpage

Publications (1)

Publication Number Publication Date
KR20120101136A true KR20120101136A (ko) 2012-09-12

Family

ID=43629207

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127018759A Abandoned KR20120101136A (ko) 2009-12-17 2010-12-17 반도체 다이 뒤틀림을 제어하기 위한 장치 및 방법

Country Status (7)

Country Link
US (1) US8710629B2 (https=)
EP (1) EP2513967A2 (https=)
JP (1) JP5536901B2 (https=)
KR (1) KR20120101136A (https=)
CN (1) CN103038877A (https=)
TW (1) TW201131717A (https=)
WO (1) WO2011084706A2 (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8378458B2 (en) * 2010-03-22 2013-02-19 Advanced Micro Devices, Inc. Semiconductor chip with a rounded corner
US8883634B2 (en) * 2011-06-29 2014-11-11 Globalfoundries Singapore Pte. Ltd. Package interconnects
US9184144B2 (en) * 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
US9059191B2 (en) * 2011-10-19 2015-06-16 International Business Machines Corporation Chamfered corner crackstop for an integrated circuit chip
US8464200B1 (en) 2012-02-15 2013-06-11 International Business Machines Corporation Thermal relief optimization
US8566773B2 (en) 2012-02-15 2013-10-22 International Business Machines Corporation Thermal relief automation
CN103378030B (zh) * 2012-04-18 2016-04-20 中芯国际集成电路制造(上海)有限公司 硅通孔结构
CN103377990B (zh) * 2012-04-18 2016-08-31 中芯国际集成电路制造(上海)有限公司 硅通孔结构
US9291578B2 (en) * 2012-08-03 2016-03-22 David L. Adler X-ray photoemission microscope for integrated devices
US9245826B2 (en) * 2013-03-11 2016-01-26 Newport Fab, Llc Anchor vias for improved backside metal adhesion to semiconductor substrate
US9247636B2 (en) 2013-03-12 2016-01-26 International Business Machines Corporation Area array device connection structures with complimentary warp characteristics
US9355967B2 (en) 2013-06-24 2016-05-31 Qualcomm Incorporated Stress compensation patterning
US9236301B2 (en) 2013-07-11 2016-01-12 Globalfoundries Inc. Customized alleviation of stresses generated by through-substrate via(S)
KR102122456B1 (ko) 2013-12-20 2020-06-12 삼성전자주식회사 실리콘 관통 비아 플러그들을 갖는 반도체 소자 및 이를 포함하는 반도체 패키지
US10006899B2 (en) 2014-03-25 2018-06-26 Genia Technologies, Inc. Nanopore-based sequencing chips using stacked wafer technology
US9728518B2 (en) 2014-04-01 2017-08-08 Ati Technologies Ulc Interconnect etch with polymer layer edge protection
US9560745B2 (en) * 2014-09-26 2017-01-31 Qualcomm Incorporated Devices and methods to reduce stress in an electronic device
US9772268B2 (en) * 2015-03-30 2017-09-26 International Business Machines Corporation Predicting semiconductor package warpage
US9721906B2 (en) * 2015-08-31 2017-08-01 Intel Corporation Electronic package with corner supports
US20170287873A1 (en) * 2016-03-29 2017-10-05 Santosh Sankarasubramanian Electronic assembly components with corner adhesive for warpage reduction during thermal processing
CN106531714A (zh) * 2017-01-24 2017-03-22 日月光封装测试(上海)有限公司 用于半导体封装的引线框架条及其制造方法
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US12424531B2 (en) 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US10396003B2 (en) * 2017-10-18 2019-08-27 Micron Technology, Inc. Stress tuned stiffeners for micro electronics package warpage control
US10861797B2 (en) * 2018-07-16 2020-12-08 Micron Technology, Inc. Electrically or temperature activated shape-memory materials for warpage control
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
US11308257B1 (en) 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
WO2026038490A1 (ja) * 2024-08-13 2026-02-19 Ａｇｃ株式会社 半導体用無機基板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2704001B2 (ja) * 1989-07-18 1998-01-26 キヤノン株式会社 位置検出装置
JP3920399B2 (ja) * 1997-04-25 2007-05-30 株式会社東芝 マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置
US6011301A (en) * 1998-06-09 2000-01-04 Stmicroelectronics, Inc. Stress reduction for flip chip package
US6372600B1 (en) * 1999-08-30 2002-04-16 Agere Systems Guardian Corp. Etch stops and alignment marks for bonded wafers
JP3895987B2 (ja) * 2001-12-27 2007-03-22 株式会社東芝 半導体装置およびその製造方法
US6897125B2 (en) * 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
JP4467318B2 (ja) * 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4768994B2 (ja) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
US7948088B2 (en) 2005-08-26 2011-05-24 Hitachi, Ltd. Semiconductor device
WO2007023950A1 (ja) 2005-08-26 2007-03-01 Hitachi, Ltd. 半導体装置の製造方法
JP4735280B2 (ja) * 2006-01-18 2011-07-27 株式会社日立製作所 パターン形成方法
JP4714049B2 (ja) * 2006-03-15 2011-06-29 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
JP5361156B2 (ja) * 2007-08-06 2013-12-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP2513967A2 (en) 2012-10-24
JP2013526001A (ja) 2013-06-20
WO2011084706A3 (en) 2013-03-28
WO2011084706A2 (en) 2011-07-14
US20110147895A1 (en) 2011-06-23
TW201131717A (en) 2011-09-16
CN103038877A (zh) 2013-04-10
US8710629B2 (en) 2014-04-29
JP5536901B2 (ja) 2014-07-02

Similar Documents

Publication Publication Date Title
KR20120101136A (ko) 반도체 다이 뒤틀림을 제어하기 위한 장치 및 방법
CN102484099B (zh) 用于不同半导体裸片和/或晶片的半导体晶片到晶片结合
US8076762B2 (en) Variable feature interface that induces a balanced stress to prevent thin die warpage
KR101309549B1 (ko) 얇은 반도체들에 대한 패널화된 후면 공정
KR102550873B1 (ko) 패키지-온-패키지 구조를 위한 인터포저
US20150221528A9 (en) Process for improving package warpage and connection reliability through use of a backside mold configuration (bsmc)
US20210375743A1 (en) Variable dielectric constant materials in same layer of a package

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

AMND Amendment
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

AMND Amendment
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PX0901 Re-examination

St.27 status event code: A-2-3-E10-E12-rex-PX0901

PX0701 Decision of registration after re-examination

St.27 status event code: A-3-4-F10-F13-rex-PX0701

X701 Decision to grant (after re-examination)
NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U14-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000