JP5498864B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP5498864B2
JP5498864B2 JP2010130422A JP2010130422A JP5498864B2 JP 5498864 B2 JP5498864 B2 JP 5498864B2 JP 2010130422 A JP2010130422 A JP 2010130422A JP 2010130422 A JP2010130422 A JP 2010130422A JP 5498864 B2 JP5498864 B2 JP 5498864B2
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Japan
Prior art keywords
film
layer
electrode
copper
tin
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JP2010130422A
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English (en)
Japanese (ja)
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JP2011258664A5 (enExample
JP2011258664A (ja
Inventor
昌宏 春原
茂明 菅沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010130422A priority Critical patent/JP5498864B2/ja
Priority to US13/153,590 priority patent/US8664536B2/en
Publication of JP2011258664A publication Critical patent/JP2011258664A/ja
Publication of JP2011258664A5 publication Critical patent/JP2011258664A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0341—Intermediate metal, e.g. before reinforcing of conductors by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2010130422A 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法 Active JP5498864B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010130422A JP5498864B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法
US13/153,590 US8664536B2 (en) 2010-06-07 2011-06-06 Wiring substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010130422A JP5498864B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2011258664A JP2011258664A (ja) 2011-12-22
JP2011258664A5 JP2011258664A5 (enExample) 2013-05-16
JP5498864B2 true JP5498864B2 (ja) 2014-05-21

Family

ID=45063591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010130422A Active JP5498864B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US8664536B2 (enExample)
JP (1) JP5498864B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5608430B2 (ja) * 2010-06-07 2014-10-15 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP2012212867A (ja) * 2011-03-30 2012-11-01 Ibiden Co Ltd プリント配線板及びその製造方法
WO2017100752A2 (en) * 2015-12-11 2017-06-15 Thin Film Electronics Asa Electronic device having a plated antenna and/or trace, and methods of making and using the same
WO2017199712A1 (ja) * 2016-05-16 2017-11-23 株式会社村田製作所 セラミック電子部品
CN111293072B (zh) * 2018-12-10 2023-06-20 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261167A (ja) * 2005-03-15 2006-09-28 Murata Mfg Co Ltd 配線基板およびその製造方法
JP5082253B2 (ja) * 2006-02-10 2012-11-28 大日本印刷株式会社 受動素子内蔵配線基板およびその製造方法
JP5231733B2 (ja) * 2006-11-27 2013-07-10 パナソニック株式会社 貫通孔配線構造およびその形成方法
JP2009238957A (ja) * 2008-03-26 2009-10-15 Panasonic Electric Works Co Ltd 基板へのビアの形成方法
JP5343245B2 (ja) * 2008-05-15 2013-11-13 新光電気工業株式会社 シリコンインターポーザの製造方法
JP2010050116A (ja) * 2008-08-19 2010-03-04 Fcm Kk 多層積層回路基板
US7741148B1 (en) * 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8248803B2 (en) * 2010-03-31 2012-08-21 Hong Kong Applied Science and Technology Research Institute Company Limited Semiconductor package and method of manufacturing the same

Also Published As

Publication number Publication date
US8664536B2 (en) 2014-03-04
JP2011258664A (ja) 2011-12-22
US20110297426A1 (en) 2011-12-08

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