JP5481724B2 - 半導体素子内蔵基板 - Google Patents

半導体素子内蔵基板 Download PDF

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Publication number
JP5481724B2
JP5481724B2 JP2009291632A JP2009291632A JP5481724B2 JP 5481724 B2 JP5481724 B2 JP 5481724B2 JP 2009291632 A JP2009291632 A JP 2009291632A JP 2009291632 A JP2009291632 A JP 2009291632A JP 5481724 B2 JP5481724 B2 JP 5481724B2
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Japan
Prior art keywords
substrate
dam
semiconductor element
pad
solder
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JP2009291632A
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English (en)
Japanese (ja)
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JP2011134818A (ja
JP2011134818A5 (https=
Inventor
洋弘 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009291632A priority Critical patent/JP5481724B2/ja
Priority to US12/971,596 priority patent/US8330277B2/en
Publication of JP2011134818A publication Critical patent/JP2011134818A/ja
Publication of JP2011134818A5 publication Critical patent/JP2011134818A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2009291632A 2009-12-24 2009-12-24 半導体素子内蔵基板 Active JP5481724B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009291632A JP5481724B2 (ja) 2009-12-24 2009-12-24 半導体素子内蔵基板
US12/971,596 US8330277B2 (en) 2009-12-24 2010-12-17 Semiconductor element built-in device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009291632A JP5481724B2 (ja) 2009-12-24 2009-12-24 半導体素子内蔵基板

Publications (3)

Publication Number Publication Date
JP2011134818A JP2011134818A (ja) 2011-07-07
JP2011134818A5 JP2011134818A5 (https=) 2012-11-08
JP5481724B2 true JP5481724B2 (ja) 2014-04-23

Family

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Family Applications (1)

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JP2009291632A Active JP5481724B2 (ja) 2009-12-24 2009-12-24 半導体素子内蔵基板

Country Status (2)

Country Link
US (1) US8330277B2 (https=)
JP (1) JP5481724B2 (https=)

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KR101811301B1 (ko) * 2011-05-24 2017-12-26 삼성전자주식회사 반도체 패키지
US8806420B2 (en) 2011-09-13 2014-08-12 Alcatel Lucent In-grid on-device decoupling for BGA
JP5893387B2 (ja) * 2011-12-22 2016-03-23 新光電気工業株式会社 電子装置及びその製造方法
JP6051577B2 (ja) * 2012-04-20 2016-12-27 セイコーエプソン株式会社 電子デバイスおよび電子機器
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
KR102694901B1 (ko) * 2012-11-20 2024-08-16 앰코 테크놀로지 싱가포르 홀딩 피티이. 엘티디. 반도체 패키지 및 그 제조 방법
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US9497861B2 (en) * 2012-12-06 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
KR20140082444A (ko) * 2012-12-24 2014-07-02 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판 제조 방법
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
US9313881B2 (en) * 2013-01-11 2016-04-12 Qualcomm Incorporated Through mold via relief gutter on molded laser package (MLP) packages
JP6230794B2 (ja) * 2013-01-31 2017-11-15 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
TWI533421B (zh) 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
JP6415111B2 (ja) * 2013-06-20 2018-10-31 キヤノン株式会社 プリント回路板、半導体装置の接合構造及びプリント回路板の製造方法
US9659891B2 (en) * 2013-09-09 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a boundary structure, a package on package structure, and a method of making
US9299650B1 (en) * 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
US9698079B2 (en) * 2014-01-03 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures between external electrical connectors
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
JP6152816B2 (ja) * 2014-03-26 2017-06-28 ソニー株式会社 半導体デバイス、表示パネル、表示装置、電子装置、および、半導体デバイスの製造方法
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JP2016115884A (ja) * 2014-12-17 2016-06-23 凸版印刷株式会社 半導体装置及びその製造方法
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Publication number Publication date
JP2011134818A (ja) 2011-07-07
US8330277B2 (en) 2012-12-11
US20110156264A1 (en) 2011-06-30

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