JP5464526B2 - ソリッドステートメモリデバイスにおけるメモリセルのアナログ検出 - Google Patents
ソリッドステートメモリデバイスにおけるメモリセルのアナログ検出 Download PDFInfo
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- JP5464526B2 JP5464526B2 JP2010517096A JP2010517096A JP5464526B2 JP 5464526 B2 JP5464526 B2 JP 5464526B2 JP 2010517096 A JP2010517096 A JP 2010517096A JP 2010517096 A JP2010517096 A JP 2010517096A JP 5464526 B2 JP5464526 B2 JP 5464526B2
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Description
本開示の実施形態は、ソリッドステートメモリデバイス、NANDフラッシュメモリ、もしくは何らかの他の種類のメモリデバイスといったメモリデバイスにおいて、メモリセルのアナログ検出を実行する。例えば、サンプル/ホールド回路は、選択されたメモリセルがプログラムされる予定のターゲット閾値電圧と、現在の閾値電圧の両方を記憶する。その後、これら二つの電圧がほぼ等しくなるまで、および/または現在の閾値電圧がターゲット閾値電圧を超え始めるまで、これら二つの電圧に対する比較が実行され得る。この時点で、選択されたセルのさらなるプログラミングは抑止される。
Claims (9)
- 選択されたメモリセルを操作するための方法であって、
ターゲット閾値電圧を表す値を有するターゲットデータを、サンプル/ホールド回路の第一の記憶デバイスに記憶することと、
前記選択されたメモリセルの閾値電圧を、該閾値電圧を表す値が前記ターゲット閾値電圧を表す値に少なくとも等しくなるまで、増加させることと、
前記閾値電圧を表す値を前記サンプル/ホールド回路の第二の記憶デバイスに記憶することと、
前記サンプル/ホールド回路が、前記記憶された前記ターゲット閾値電圧を表す値と、前記記憶された前記閾値電圧を表す値とを比較することと、
前記比較の結果に応じて、前記閾値電圧の前記増加を抑止するか又は減速させることと、
を含む方法。 - 前記ターゲット閾値電圧を表す値と前記閾値電圧を表す値が、それぞれ前記ターゲット閾値電圧と前記閾値電圧をレベルシフトしたものである、請求項1に記載の方法。
- 前記閾値電圧を増加させることが、複数のプログラミングパルスを生成することを含み、各パルスはその前のパルスよりも漸増した電圧を有する、請求項1に記載の方法。
- 前記選択されたメモリセルを読み出して前記閾値電圧を決定することをさらに含み、前記選択されたメモリセルを読み出すことは、前記選択されたメモリセルが前記閾値電圧でオンになるよう、前記選択されたメモリセルに結合されたワード線にランプ読み出し電圧でバイアスをかけることを含む、請求項1に記載の方法。
- 前記選択されたメモリセルに第一のプログラミング電圧でバイアスをかけることにより、前記選択されたメモリセルの前記閾値電圧を増加させることと、
第一の閾値電圧を決定するために前記選択されたメモリセルを検証することと、
前記第一の閾値電圧を表す値を前記サンプル/ホールド回路の前記第二の記憶デバイスに記憶することと、
前記サンプル/ホールド回路が、前記ターゲット閾値電圧を表す値を前記第一の閾値電圧を表す値と比較することと、
前記ターゲット閾値電圧を表す値が前記第一の閾値電圧を表す値と等しい場合、前記選択されたメモリセルのプログラミングを抑止することと、
をさらに含む、請求項1に記載の方法。 - 前記選択されたメモリセルを検証することが、前記選択されたメモリセルの制御ゲートにランプ読み出し電圧でバイアスをかけることを含む、請求項5に記載の方法。
- 前記第一の閾値電圧を決定することが、
前記ランプ読み出し電圧に応じてビット線の電流を監視することと、
前記電流が発生するときを決定することと、
前記電流を発生させる前記ランプ読み出し電圧の電圧を決定することと、
を含む、請求項6に記載の方法。 - 前記第一の閾値電圧を表す値が前記ターゲット閾値電圧を表す値に等しくなるまで、前記選択されたメモリセルに、漸増するプログラミング電圧でバイアスをかけることをさらに含む、請求項5に記載の方法。
- 前記ターゲット閾値電圧を表す値が、前記選択されたメモリセルにプログラムされる予定のターゲットデータである、請求項5に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/879,907 US7898885B2 (en) | 2007-07-19 | 2007-07-19 | Analog sensing of memory cells in a solid state memory device |
US11/879,907 | 2007-07-19 | ||
PCT/US2008/069949 WO2009012209A1 (en) | 2007-07-19 | 2008-07-14 | Analog sensing of memory cells in a solid-state memory device |
Related Child Applications (1)
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JP2013033622A Division JP5534064B2 (ja) | 2007-07-19 | 2013-02-22 | ソリッドステートメモリデバイスにおけるメモリセルのアナログ検出 |
Publications (2)
Publication Number | Publication Date |
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JP2010533930A JP2010533930A (ja) | 2010-10-28 |
JP5464526B2 true JP5464526B2 (ja) | 2014-04-09 |
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JP2010517096A Active JP5464526B2 (ja) | 2007-07-19 | 2008-07-14 | ソリッドステートメモリデバイスにおけるメモリセルのアナログ検出 |
JP2013033622A Active JP5534064B2 (ja) | 2007-07-19 | 2013-02-22 | ソリッドステートメモリデバイスにおけるメモリセルのアナログ検出 |
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Country Status (7)
Country | Link |
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US (2) | US7898885B2 (ja) |
EP (2) | EP2469539A1 (ja) |
JP (2) | JP5464526B2 (ja) |
KR (1) | KR20100034045A (ja) |
CN (2) | CN103730166B (ja) |
TW (1) | TWI390539B (ja) |
WO (1) | WO2009012209A1 (ja) |
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2007
- 2007-07-19 US US11/879,907 patent/US7898885B2/en active Active
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2008
- 2008-07-14 CN CN201410036255.3A patent/CN103730166B/zh active Active
- 2008-07-14 KR KR1020107003560A patent/KR20100034045A/ko not_active Application Discontinuation
- 2008-07-14 EP EP12001345A patent/EP2469539A1/en not_active Withdrawn
- 2008-07-14 CN CN200880025242.9A patent/CN101755305B/zh active Active
- 2008-07-14 EP EP08781790.4A patent/EP2171720B1/en active Active
- 2008-07-14 WO PCT/US2008/069949 patent/WO2009012209A1/en active Application Filing
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EP2171720B1 (en) | 2013-08-21 |
JP5534064B2 (ja) | 2014-06-25 |
EP2469539A1 (en) | 2012-06-27 |
JP2013152777A (ja) | 2013-08-08 |
CN101755305B (zh) | 2014-03-12 |
US20090021987A1 (en) | 2009-01-22 |
TWI390539B (zh) | 2013-03-21 |
US8976582B2 (en) | 2015-03-10 |
KR20100034045A (ko) | 2010-03-31 |
CN101755305A (zh) | 2010-06-23 |
US7898885B2 (en) | 2011-03-01 |
CN103730166B (zh) | 2017-04-12 |
JP2010533930A (ja) | 2010-10-28 |
CN103730166A (zh) | 2014-04-16 |
TW200915329A (en) | 2009-04-01 |
WO2009012209A1 (en) | 2009-01-22 |
EP2171720A4 (en) | 2010-08-04 |
EP2171720A1 (en) | 2010-04-07 |
US20110128790A1 (en) | 2011-06-02 |
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