JP5459959B2 - マルチチップ・ウェハレベル・パッケージを形成する方法 - Google Patents

マルチチップ・ウェハレベル・パッケージを形成する方法 Download PDF

Info

Publication number
JP5459959B2
JP5459959B2 JP2007541952A JP2007541952A JP5459959B2 JP 5459959 B2 JP5459959 B2 JP 5459959B2 JP 2007541952 A JP2007541952 A JP 2007541952A JP 2007541952 A JP2007541952 A JP 2007541952A JP 5459959 B2 JP5459959 B2 JP 5459959B2
Authority
JP
Japan
Prior art keywords
chip
chips
wafer
forming
carrier substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007541952A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008521228A (ja
JP2008521228A5 (enExample
Inventor
バレル、ロイド
チェン、ハワード、ハオ
シュー、ルイス
ソーター、ウルフガング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2008521228A publication Critical patent/JP2008521228A/ja
Publication of JP2008521228A5 publication Critical patent/JP2008521228A5/ja
Application granted granted Critical
Publication of JP5459959B2 publication Critical patent/JP5459959B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2007541952A 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法 Expired - Fee Related JP5459959B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/994,494 US7405108B2 (en) 2004-11-20 2004-11-20 Methods for forming co-planar wafer-scale chip packages
US10/994,494 2004-11-20
PCT/EP2005/056009 WO2006053879A1 (en) 2004-11-20 2005-11-16 Methods for forming co-planar wafer-scale chip packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011160519A Division JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Publications (3)

Publication Number Publication Date
JP2008521228A JP2008521228A (ja) 2008-06-19
JP2008521228A5 JP2008521228A5 (enExample) 2008-10-02
JP5459959B2 true JP5459959B2 (ja) 2014-04-02

Family

ID=35735294

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2007541952A Expired - Fee Related JP5459959B2 (ja) 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法
JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Country Status (9)

Country Link
US (2) US7405108B2 (enExample)
EP (1) EP1817793B1 (enExample)
JP (2) JP5459959B2 (enExample)
KR (1) KR100992015B1 (enExample)
CN (1) CN100437952C (enExample)
AT (1) ATE477588T1 (enExample)
DE (1) DE602005022919D1 (enExample)
TW (1) TWI362706B (enExample)
WO (1) WO2006053879A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
US7442579B2 (en) * 2004-11-22 2008-10-28 International Business Machines Corporation Methods to achieve precision alignment for wafer scale packages
DE102005039479B3 (de) * 2005-08-18 2007-03-29 Infineon Technologies Ag Halbleiterbauteil mit gedünntem Halbleiterchip und Verfahren zur Herstellung des gedünnten Halbleiterbauteils
US7658901B2 (en) * 2005-10-14 2010-02-09 The Trustees Of Princeton University Thermally exfoliated graphite oxide
JP4559993B2 (ja) * 2006-03-29 2010-10-13 株式会社東芝 半導体装置の製造方法
KR100829392B1 (ko) * 2006-08-24 2008-05-13 동부일렉트로닉스 주식회사 ＳｏＣ 및 그 제조 방법
TW200941661A (en) * 2008-03-19 2009-10-01 Integrated Circuit Solution Inc Shape of window formed in a substrate for window ball grid array package
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
US8322022B1 (en) 2010-06-28 2012-12-04 Western Digital (Fremont), Llc Method for providing an energy assisted magnetic recording head in a wafer packaging configuration
CN102386088B (zh) * 2010-09-03 2014-06-25 中芯国际集成电路制造(上海)有限公司 用于去除半导体器件结构上的光致抗蚀剂层的方法
CN102769002B (zh) * 2011-04-30 2016-09-14 中国科学院微电子研究所 半导体器件及其形成方法、封装结构
JP6063641B2 (ja) * 2012-05-16 2017-01-18 株式会社ディスコ ウエーハ保護部材
US20150380369A1 (en) * 2013-09-30 2015-12-31 Nantong Fujitsu Microelectronics Co., Ltd Wafer packaging structure and packaging method
US9123546B2 (en) * 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
US9350339B2 (en) 2014-07-18 2016-05-24 Qualcomm Incorporated Systems and methods for clock distribution in a die-to-die interface
JP6341959B2 (ja) 2016-05-27 2018-06-13 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
CN109196405B (zh) 2016-05-27 2021-09-10 浜松光子学株式会社 法布里-帕罗干涉滤光器的制造方法
KR102508597B1 (ko) 2016-08-24 2023-03-13 하마마츠 포토닉스 가부시키가이샤 패브리 페로 간섭 필터
US10916507B2 (en) 2018-12-04 2021-02-09 International Business Machines Corporation Multiple chip carrier for bridge assembly
GB2582384B (en) * 2019-03-22 2023-10-18 Cirrus Logic Int Semiconductor Ltd Semiconductor structures
US11456247B2 (en) * 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
CN110690868B (zh) * 2019-09-27 2021-02-19 无锡市好达电子股份有限公司 一种滤波器的新型晶圆级封装方法
CN111128716B (zh) * 2019-11-15 2023-10-17 西安电子科技大学 一种大面积图形自对准的异质集成方法
KR102766434B1 (ko) 2020-03-26 2025-02-12 삼성전자주식회사 반도체 스택 및 그 제조 방법
TWI790003B (zh) * 2021-11-18 2023-01-11 佳邦科技股份有限公司 過電壓保護元件

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281745A (ja) 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
US4866501A (en) * 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US5091331A (en) 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding
JPH0645436A (ja) * 1992-07-22 1994-02-18 Nec Corp 半導体基板の貼付方法
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
JPH0878487A (ja) * 1994-08-31 1996-03-22 Nec Kyushu Ltd 半導体基板および半導体装置の製造方法
US5770884A (en) * 1995-06-30 1998-06-23 International Business Machines Corporation Very dense integrated circuit package
US5880007A (en) * 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
US6177299B1 (en) * 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
JPH11354667A (ja) * 1998-06-05 1999-12-24 Nippon Telegr & Teleph Corp <Ntt> 電子部品およびその実装方法
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
JP2003197850A (ja) * 2001-12-26 2003-07-11 Sony Corp 半導体装置及びその製造方法
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US7203393B2 (en) * 2002-03-08 2007-04-10 Movaz Networks, Inc. MEMS micro mirrors driven by electrodes fabricated on another substrate
DE60335554D1 (de) * 2002-05-20 2011-02-10 Imagerlabs Inc Bilden einer integrierten mehrsegmentschaltung mit isolierten substraten
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7078320B2 (en) * 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7005319B1 (en) * 2004-11-19 2006-02-28 International Business Machines Corporation Global planarization of wafer scale package with precision die thickness control
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages

Also Published As

Publication number Publication date
CN100437952C (zh) 2008-11-26
DE602005022919D1 (de) 2010-09-23
KR100992015B1 (ko) 2010-11-05
US20080280399A1 (en) 2008-11-13
ATE477588T1 (de) 2010-08-15
TW200633081A (en) 2006-09-16
US7867820B2 (en) 2011-01-11
EP1817793B1 (en) 2010-08-11
JP2011249830A (ja) 2011-12-08
EP1817793A1 (en) 2007-08-15
WO2006053879A1 (en) 2006-05-26
CN101027765A (zh) 2007-08-29
US20060110851A1 (en) 2006-05-25
JP5474002B2 (ja) 2014-04-16
KR20070085402A (ko) 2007-08-27
TWI362706B (en) 2012-04-21
US7405108B2 (en) 2008-07-29
JP2008521228A (ja) 2008-06-19

Similar Documents

Publication Publication Date Title
JP5474002B2 (ja) マルチチップ・ウェハレベル・パッケージを形成する方法
CN109411443B (zh) 垂直堆叠晶圆及其形成方法
US10011098B2 (en) Four D device process and structure
US7098070B2 (en) Device and method for fabricating double-sided SOI wafer scale package with through via connections
JP5246831B2 (ja) 電子デバイス及びそれを形成する方法
TWI478282B (zh) 半導體元件的形成方法
JP3986575B2 (ja) ３次元集積回路の製造方法
CN110892521B (zh) 用于裸片对裸片进行键合的方法和结构
JP2008521228A5 (enExample)
US10818570B1 (en) Stacked semiconductor devices having dissimilar-sized dies
EP3171399B1 (en) Method for singulating a stack of semiconductor wafers
CN113921467A (zh) 用于半导体裸片边缘防护和半导体裸片分离的方法
CN102084479A (zh) 具有互连的晶圆级集成模块
US20250349752A1 (en) Semiconductor packages and methods of manufacturing thereof
EP4338198B1 (en) Method of manufacturing active reconstructed wafers
US20250118564A1 (en) Method for Thinning a Semiconductor Substrate
TWI895092B (zh) 半導體超薄堆疊結構的製造方法
JP2025514785A (ja) 誘電体アライメントマーク及びレーザリフトオフプロセスを使用して半導体パッケージを形成する方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080813

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080813

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110414

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110426

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110722

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110823

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111115

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120731

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20121119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121120

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20121120

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20121120

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20121213

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20130118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131029

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140114

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees