KR100992015B1 - 동일 평면의 웨이퍼-스케일 칩 패키지들을 형성하는 방법 - Google Patents

동일 평면의 웨이퍼-스케일 칩 패키지들을 형성하는 방법 Download PDF

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KR100992015B1
KR100992015B1 KR1020077011373A KR20077011373A KR100992015B1 KR 100992015 B1 KR100992015 B1 KR 100992015B1 KR 1020077011373 A KR1020077011373 A KR 1020077011373A KR 20077011373 A KR20077011373 A KR 20077011373A KR 100992015 B1 KR100992015 B1 KR 100992015B1
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chip
chips
wafer
regions
forming
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Korean (ko)
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KR20070085402A (ko
Inventor
로이드 버렐
호워드 하오 첸
루이스 휴
볼프강 사우터
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인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
KR1020077011373A 2004-11-20 2005-11-16 동일 평면의 웨이퍼-스케일 칩 패키지들을 형성하는 방법 Expired - Fee Related KR100992015B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/994,494 US7405108B2 (en) 2004-11-20 2004-11-20 Methods for forming co-planar wafer-scale chip packages
US10/994,494 2004-11-20

Publications (2)

Publication Number Publication Date
KR20070085402A KR20070085402A (ko) 2007-08-27
KR100992015B1 true KR100992015B1 (ko) 2010-11-05

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KR1020077011373A Expired - Fee Related KR100992015B1 (ko) 2004-11-20 2005-11-16 동일 평면의 웨이퍼-스케일 칩 패키지들을 형성하는 방법

Country Status (9)

Country Link
US (2) US7405108B2 (enExample)
EP (1) EP1817793B1 (enExample)
JP (2) JP5459959B2 (enExample)
KR (1) KR100992015B1 (enExample)
CN (1) CN100437952C (enExample)
AT (1) ATE477588T1 (enExample)
DE (1) DE602005022919D1 (enExample)
TW (1) TWI362706B (enExample)
WO (1) WO2006053879A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
US7442579B2 (en) * 2004-11-22 2008-10-28 International Business Machines Corporation Methods to achieve precision alignment for wafer scale packages
DE102005039479B3 (de) * 2005-08-18 2007-03-29 Infineon Technologies Ag Halbleiterbauteil mit gedünntem Halbleiterchip und Verfahren zur Herstellung des gedünnten Halbleiterbauteils
US7658901B2 (en) * 2005-10-14 2010-02-09 The Trustees Of Princeton University Thermally exfoliated graphite oxide
JP4559993B2 (ja) * 2006-03-29 2010-10-13 株式会社東芝 半導体装置の製造方法
KR100829392B1 (ko) * 2006-08-24 2008-05-13 동부일렉트로닉스 주식회사 ＳｏＣ 및 그 제조 방법
TW200941661A (en) * 2008-03-19 2009-10-01 Integrated Circuit Solution Inc Shape of window formed in a substrate for window ball grid array package
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
US8322022B1 (en) 2010-06-28 2012-12-04 Western Digital (Fremont), Llc Method for providing an energy assisted magnetic recording head in a wafer packaging configuration
CN102386088B (zh) * 2010-09-03 2014-06-25 中芯国际集成电路制造(上海)有限公司 用于去除半导体器件结构上的光致抗蚀剂层的方法
CN102769002B (zh) * 2011-04-30 2016-09-14 中国科学院微电子研究所 半导体器件及其形成方法、封装结构
JP6063641B2 (ja) * 2012-05-16 2017-01-18 株式会社ディスコ ウエーハ保護部材
WO2015043495A1 (zh) * 2013-09-30 2015-04-02 南通富士通微电子股份有限公司 晶圆封装结构和封装方法
US9123546B2 (en) 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
US9350339B2 (en) 2014-07-18 2016-05-24 Qualcomm Incorporated Systems and methods for clock distribution in a die-to-die interface
JP6341959B2 (ja) 2016-05-27 2018-06-13 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
JP7018873B2 (ja) 2016-05-27 2022-02-14 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
JP6861213B2 (ja) 2016-08-24 2021-04-21 浜松ホトニクス株式会社 ファブリペロー干渉フィルタ
US10916507B2 (en) 2018-12-04 2021-02-09 International Business Machines Corporation Multiple chip carrier for bridge assembly
GB2582384B (en) * 2019-03-22 2023-10-18 Cirrus Logic Int Semiconductor Ltd Semiconductor structures
US11456247B2 (en) * 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
CN110690868B (zh) * 2019-09-27 2021-02-19 无锡市好达电子股份有限公司 一种滤波器的新型晶圆级封装方法
CN111128716B (zh) * 2019-11-15 2023-10-17 西安电子科技大学 一种大面积图形自对准的异质集成方法
KR102766434B1 (ko) 2020-03-26 2025-02-12 삼성전자주식회사 반도체 스택 및 그 제조 방법
TWI790003B (zh) * 2021-11-18 2023-01-11 佳邦科技股份有限公司 過電壓保護元件

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040043533A1 (en) * 2002-08-27 2004-03-04 Chua Swee Kwang Multi-chip wafer level system packages and methods of forming same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281745A (ja) 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
US4866501A (en) * 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US5091331A (en) 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding
JPH0645436A (ja) * 1992-07-22 1994-02-18 Nec Corp 半導体基板の貼付方法
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
JPH0878487A (ja) * 1994-08-31 1996-03-22 Nec Kyushu Ltd 半導体基板および半導体装置の製造方法
US5770884A (en) * 1995-06-30 1998-06-23 International Business Machines Corporation Very dense integrated circuit package
US5880007A (en) * 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
US6177299B1 (en) * 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
JPH11354667A (ja) * 1998-06-05 1999-12-24 Nippon Telegr & Teleph Corp <Ntt> 電子部品およびその実装方法
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
JP2003197850A (ja) * 2001-12-26 2003-07-11 Sony Corp 半導体装置及びその製造方法
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US7203393B2 (en) * 2002-03-08 2007-04-10 Movaz Networks, Inc. MEMS micro mirrors driven by electrodes fabricated on another substrate
ATE493760T1 (de) * 2002-05-20 2011-01-15 Imagerlabs Inc Bilden einer integrierten mehrsegmentschaltung mit isolierten substraten
US7078320B2 (en) * 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7005319B1 (en) * 2004-11-19 2006-02-28 International Business Machines Corporation Global planarization of wafer scale package with precision die thickness control
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040043533A1 (en) * 2002-08-27 2004-03-04 Chua Swee Kwang Multi-chip wafer level system packages and methods of forming same

Also Published As

Publication number Publication date
JP2011249830A (ja) 2011-12-08
CN100437952C (zh) 2008-11-26
TWI362706B (en) 2012-04-21
JP5474002B2 (ja) 2014-04-16
US20080280399A1 (en) 2008-11-13
JP5459959B2 (ja) 2014-04-02
US7405108B2 (en) 2008-07-29
KR20070085402A (ko) 2007-08-27
TW200633081A (en) 2006-09-16
DE602005022919D1 (de) 2010-09-23
EP1817793B1 (en) 2010-08-11
WO2006053879A1 (en) 2006-05-26
US7867820B2 (en) 2011-01-11
CN101027765A (zh) 2007-08-29
JP2008521228A (ja) 2008-06-19
ATE477588T1 (de) 2010-08-15
US20060110851A1 (en) 2006-05-25
EP1817793A1 (en) 2007-08-15

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