JP2008521228A5 - - Google Patents

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Publication number
JP2008521228A5
JP2008521228A5 JP2007541952A JP2007541952A JP2008521228A5 JP 2008521228 A5 JP2008521228 A5 JP 2008521228A5 JP 2007541952 A JP2007541952 A JP 2007541952A JP 2007541952 A JP2007541952 A JP 2007541952A JP 2008521228 A5 JP2008521228 A5 JP 2008521228A5
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JP
Japan
Prior art keywords
chip
wafer
forming
chips
area
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Application number
JP2007541952A
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English (en)
Japanese (ja)
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JP5459959B2 (ja
JP2008521228A (ja
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Priority claimed from US10/994,494 external-priority patent/US7405108B2/en
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Publication of JP2008521228A publication Critical patent/JP2008521228A/ja
Publication of JP2008521228A5 publication Critical patent/JP2008521228A5/ja
Application granted granted Critical
Publication of JP5459959B2 publication Critical patent/JP5459959B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007541952A 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法 Expired - Fee Related JP5459959B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/994,494 US7405108B2 (en) 2004-11-20 2004-11-20 Methods for forming co-planar wafer-scale chip packages
US10/994,494 2004-11-20
PCT/EP2005/056009 WO2006053879A1 (en) 2004-11-20 2005-11-16 Methods for forming co-planar wafer-scale chip packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011160519A Division JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Publications (3)

Publication Number Publication Date
JP2008521228A JP2008521228A (ja) 2008-06-19
JP2008521228A5 true JP2008521228A5 (enExample) 2008-10-02
JP5459959B2 JP5459959B2 (ja) 2014-04-02

Family

ID=35735294

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2007541952A Expired - Fee Related JP5459959B2 (ja) 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法
JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Country Status (9)

Country Link
US (2) US7405108B2 (enExample)
EP (1) EP1817793B1 (enExample)
JP (2) JP5459959B2 (enExample)
KR (1) KR100992015B1 (enExample)
CN (1) CN100437952C (enExample)
AT (1) ATE477588T1 (enExample)
DE (1) DE602005022919D1 (enExample)
TW (1) TWI362706B (enExample)
WO (1) WO2006053879A1 (enExample)

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* Cited by examiner, † Cited by third party
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US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
US7442579B2 (en) * 2004-11-22 2008-10-28 International Business Machines Corporation Methods to achieve precision alignment for wafer scale packages
DE102005039479B3 (de) * 2005-08-18 2007-03-29 Infineon Technologies Ag Halbleiterbauteil mit gedünntem Halbleiterchip und Verfahren zur Herstellung des gedünnten Halbleiterbauteils
US7658901B2 (en) * 2005-10-14 2010-02-09 The Trustees Of Princeton University Thermally exfoliated graphite oxide
JP4559993B2 (ja) * 2006-03-29 2010-10-13 株式会社東芝 半導体装置の製造方法
KR100829392B1 (ko) * 2006-08-24 2008-05-13 동부일렉트로닉스 주식회사 ＳｏＣ 및 그 제조 방법
TW200941661A (en) * 2008-03-19 2009-10-01 Integrated Circuit Solution Inc Shape of window formed in a substrate for window ball grid array package
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
US8322022B1 (en) 2010-06-28 2012-12-04 Western Digital (Fremont), Llc Method for providing an energy assisted magnetic recording head in a wafer packaging configuration
CN102386088B (zh) * 2010-09-03 2014-06-25 中芯国际集成电路制造(上海)有限公司 用于去除半导体器件结构上的光致抗蚀剂层的方法
CN102769002B (zh) * 2011-04-30 2016-09-14 中国科学院微电子研究所 半导体器件及其形成方法、封装结构
JP6063641B2 (ja) * 2012-05-16 2017-01-18 株式会社ディスコ ウエーハ保護部材
WO2015043495A1 (zh) * 2013-09-30 2015-04-02 南通富士通微电子股份有限公司 晶圆封装结构和封装方法
US9123546B2 (en) 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
US9350339B2 (en) 2014-07-18 2016-05-24 Qualcomm Incorporated Systems and methods for clock distribution in a die-to-die interface
JP6341959B2 (ja) 2016-05-27 2018-06-13 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
JP7018873B2 (ja) 2016-05-27 2022-02-14 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
JP6861213B2 (ja) 2016-08-24 2021-04-21 浜松ホトニクス株式会社 ファブリペロー干渉フィルタ
US10916507B2 (en) 2018-12-04 2021-02-09 International Business Machines Corporation Multiple chip carrier for bridge assembly
GB2582384B (en) * 2019-03-22 2023-10-18 Cirrus Logic Int Semiconductor Ltd Semiconductor structures
US11456247B2 (en) * 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
CN110690868B (zh) * 2019-09-27 2021-02-19 无锡市好达电子股份有限公司 一种滤波器的新型晶圆级封装方法
CN111128716B (zh) * 2019-11-15 2023-10-17 西安电子科技大学 一种大面积图形自对准的异质集成方法
KR102766434B1 (ko) 2020-03-26 2025-02-12 삼성전자주식회사 반도체 스택 및 그 제조 방법
TWI790003B (zh) * 2021-11-18 2023-01-11 佳邦科技股份有限公司 過電壓保護元件

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US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages

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