JP2009076915A5 - - Google Patents

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Publication number
JP2009076915A5
JP2009076915A5 JP2008241065A JP2008241065A JP2009076915A5 JP 2009076915 A5 JP2009076915 A5 JP 2009076915A5 JP 2008241065 A JP2008241065 A JP 2008241065A JP 2008241065 A JP2008241065 A JP 2008241065A JP 2009076915 A5 JP2009076915 A5 JP 2009076915A5
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JP
Japan
Prior art keywords
adhesive
substrate
bonding method
functional layer
space
Prior art date
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Application number
JP2008241065A
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English (en)
Japanese (ja)
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JP5557436B2 (ja
JP2009076915A (ja
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Publication date
Priority claimed from FR0757676A external-priority patent/FR2921201B1/fr
Application filed filed Critical
Publication of JP2009076915A publication Critical patent/JP2009076915A/ja
Publication of JP2009076915A5 publication Critical patent/JP2009076915A5/ja
Application granted granted Critical
Publication of JP5557436B2 publication Critical patent/JP5557436B2/ja
Active legal-status Critical Current
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JP2008241065A 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法 Active JP5557436B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0757676A FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur
FR0757676 2007-09-19

Publications (3)

Publication Number Publication Date
JP2009076915A JP2009076915A (ja) 2009-04-09
JP2009076915A5 true JP2009076915A5 (enExample) 2011-11-04
JP5557436B2 JP5557436B2 (ja) 2014-07-23

Family

ID=39271531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008241065A Active JP5557436B2 (ja) 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法

Country Status (4)

Country Link
US (1) US7645686B2 (enExample)
EP (1) EP2040291B1 (enExample)
JP (1) JP5557436B2 (enExample)
FR (1) FR2921201B1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961519B1 (fr) 2010-06-18 2012-07-06 Commissariat Energie Atomique Procede de collage calibre en epaisseur entre au moins deux substrats
US10374000B2 (en) 2013-09-23 2019-08-06 Teledyne Scientific & Imaging, Llc Thermal-contraction matched hybrid device package

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365088A (en) 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
JPH02271558A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4943491A (en) * 1989-11-20 1990-07-24 Honeywell Inc. Structure for improving interconnect reliability of focal plane arrays
JP2564694B2 (ja) * 1990-09-10 1996-12-18 ローム株式会社 半導体素子の製造方法
EP0829907A1 (en) 1996-09-16 1998-03-18 Rockwell International Corporation Hybrid focal plane array comprising stabilizing structure
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
US6255140B1 (en) * 1998-10-19 2001-07-03 Industrial Technology Research Institute Flip chip chip-scale package
FR2810454B1 (fr) * 2000-06-15 2003-07-18 Sofradir Detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et procede pour la realisation d'un tel detecteur
US6407381B1 (en) * 2000-07-05 2002-06-18 Amkor Technology, Inc. Wafer scale image sensor package
JP3719921B2 (ja) * 2000-09-29 2005-11-24 株式会社東芝 半導体装置及びその製造方法
TW522531B (en) * 2000-10-20 2003-03-01 Matsushita Electric Industrial Co Ltd Semiconductor device, method of manufacturing the device and mehtod of mounting the device
JP5022552B2 (ja) * 2002-09-26 2012-09-12 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
FR2857508B1 (fr) * 2003-07-09 2005-09-09 Fr De Detecteurs Infrarouges S Procede pour la realisation d'un detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et detecteur ontenu au moyen de ce procede
JP4396472B2 (ja) * 2004-10-06 2010-01-13 パナソニック株式会社 薄膜状素子の転写方法
JP4745073B2 (ja) * 2006-02-03 2011-08-10 シチズン電子株式会社 表面実装型発光素子の製造方法
TWI463580B (zh) * 2007-06-19 2014-12-01 瑞薩科技股份有限公司 Manufacturing method of semiconductor integrated circuit device

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