JP5557436B2 - チップ形成方法、及び、チップを基板にボンディングする方法 - Google Patents

チップ形成方法、及び、チップを基板にボンディングする方法 Download PDF

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JP5557436B2
JP5557436B2 JP2008241065A JP2008241065A JP5557436B2 JP 5557436 B2 JP5557436 B2 JP 5557436B2 JP 2008241065 A JP2008241065 A JP 2008241065A JP 2008241065 A JP2008241065 A JP 2008241065A JP 5557436 B2 JP5557436 B2 JP 5557436B2
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substrate
chip
adhesive
bonding
space
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JP2009076915A (ja
JP2009076915A5 (enExample
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マニュエル フェンドラー
アブドナセール エ−マニ
アラン ググノー
フランソワ マリオン
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コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Micromachines (AREA)
  • Solid State Image Pick-Up Elements (AREA)
JP2008241065A 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法 Active JP5557436B2 (ja)

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Application Number Priority Date Filing Date Title
FR0757676A FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur
FR0757676 2007-09-19

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JP2009076915A JP2009076915A (ja) 2009-04-09
JP2009076915A5 JP2009076915A5 (enExample) 2011-11-04
JP5557436B2 true JP5557436B2 (ja) 2014-07-23

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US (1) US7645686B2 (enExample)
EP (1) EP2040291B1 (enExample)
JP (1) JP5557436B2 (enExample)
FR (1) FR2921201B1 (enExample)

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FR2961519B1 (fr) 2010-06-18 2012-07-06 Commissariat Energie Atomique Procede de collage calibre en epaisseur entre au moins deux substrats
US10374000B2 (en) 2013-09-23 2019-08-06 Teledyne Scientific & Imaging, Llc Thermal-contraction matched hybrid device package

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US5365088A (en) 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
JPH02271558A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4943491A (en) * 1989-11-20 1990-07-24 Honeywell Inc. Structure for improving interconnect reliability of focal plane arrays
JP2564694B2 (ja) * 1990-09-10 1996-12-18 ローム株式会社 半導体素子の製造方法
EP0829907A1 (en) 1996-09-16 1998-03-18 Rockwell International Corporation Hybrid focal plane array comprising stabilizing structure
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
US6255140B1 (en) * 1998-10-19 2001-07-03 Industrial Technology Research Institute Flip chip chip-scale package
FR2810454B1 (fr) * 2000-06-15 2003-07-18 Sofradir Detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et procede pour la realisation d'un tel detecteur
US6407381B1 (en) * 2000-07-05 2002-06-18 Amkor Technology, Inc. Wafer scale image sensor package
JP3719921B2 (ja) * 2000-09-29 2005-11-24 株式会社東芝 半導体装置及びその製造方法
TW522531B (en) * 2000-10-20 2003-03-01 Matsushita Electric Industrial Co Ltd Semiconductor device, method of manufacturing the device and mehtod of mounting the device
JP5022552B2 (ja) * 2002-09-26 2012-09-12 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
FR2857508B1 (fr) * 2003-07-09 2005-09-09 Fr De Detecteurs Infrarouges S Procede pour la realisation d'un detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et detecteur ontenu au moyen de ce procede
JP4396472B2 (ja) * 2004-10-06 2010-01-13 パナソニック株式会社 薄膜状素子の転写方法
JP4745073B2 (ja) * 2006-02-03 2011-08-10 シチズン電子株式会社 表面実装型発光素子の製造方法
TWI463580B (zh) * 2007-06-19 2014-12-01 瑞薩科技股份有限公司 Manufacturing method of semiconductor integrated circuit device

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EP2040291A1 (fr) 2009-03-25
FR2921201A1 (fr) 2009-03-20
FR2921201B1 (fr) 2009-12-18
EP2040291B1 (fr) 2018-03-14
US20090075423A1 (en) 2009-03-19
JP2009076915A (ja) 2009-04-09
US7645686B2 (en) 2010-01-12

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