JP5458709B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5458709B2 JP5458709B2 JP2009164450A JP2009164450A JP5458709B2 JP 5458709 B2 JP5458709 B2 JP 5458709B2 JP 2009164450 A JP2009164450 A JP 2009164450A JP 2009164450 A JP2009164450 A JP 2009164450A JP 5458709 B2 JP5458709 B2 JP 5458709B2
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- 239000004065 semiconductor Substances 0.000 title claims description 162
- 239000004020 conductor Substances 0.000 claims description 133
- 239000012535 impurity Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 48
- 230000015556 catabolic process Effects 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 12
- 230000005684 electric field Effects 0.000 description 36
- 230000000694 effects Effects 0.000 description 31
- 238000012986 modification Methods 0.000 description 24
- 230000004048 modification Effects 0.000 description 24
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 21
- 239000003990 capacitor Substances 0.000 description 21
- 230000000052 comparative effect Effects 0.000 description 12
- 239000012141 concentrate Substances 0.000 description 8
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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Description
以下に、実施の形態1に係る半導体装置の構成について説明する。図1は、実施の形態1に係る半導体装置の上面図である。図2は、図1に示すA−A´を通る半導体装置の断面を示す図である。
不純物添加領域12は、エピタキシャル法により形成された不純物添加層である。半絶縁性GaAs基板10の上面側において、不純物添加領域12の周囲には絶縁領域14が設けられている。絶縁領域14は、エピタキシャル法により形成した不純物添加層に、B+、H+、He、Oなどをイオン注入することによって形成されたものである。
以下に、実施の形態2に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図5は、実施の形態2に係る半導体装置の上面図である。導体46は不純物添加領域12を取囲むように設けられている。つまり、ソース電極18から絶縁領域14を介してドレインパッド38に至る経路の全てに、導体46が設けられている。
以下に、実施の形態3に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図6は、実施の形態3に係る半導体装置の上面図である。導体46はゲート配線32の両端と接続し、ゲート配線32を介してゲート電極16と接続している。このため、導体46の電位Vは、ゲート電極16の電位に設定される。
以下に、実施の形態4に係る半導体装置の構成及び効果について、実施の形態3とは異なる点のみを説明する。図7は、実施の形態4に係る半導体装置の上面図である。導体46及びゲート電極16の複数組のそれぞれが、ゲート配線32とともにソース電極18を取囲むように、リング形状に一体形成されている。
以下に、実施の形態5に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図8は、実施の形態5に係る半導体装置の上面図である。導体46はソースパッド30を介してソース電極18と接続している。このため、導体46の電位はソース電極18の電位に設定される。
以下に、実施の形態6に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図9は、実施の形態6に係る半導体装置の上面図である。
以下に、実施の形態7に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図10は、実施の形態7に係る半導体装置において、図1に示すA−A´と対応する部分を通る断面を示す図である。
以下に、実施の形態8に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図11は、実施の形態8に係る半導体装置において、図1に示すA−A´と対応する部分を通る断面を示す図である。
以下に、実施の形態9に係る半導体装置の構成及び効果について、実施の形態8とは異なる点のみを説明する。図12は、実施の形態9に係る半導体装置において、図1に示すA−A´と対応する部分を通る断面を示す図である。
以下に、実施の形態10に係る半導体装置の構成及び効果について、実施の形態1とは異なる点のみを説明する。図13は、実施の形態10に係る半導体装置において、図1に示すA−A´と対応する部分を通る断面を示す図である。
以下に、実施の形態11に係る半導体装置の構成について、実施の形態1とは異なる点のみを説明する。図14は、実施の形態11に係る半導体装置の上面図である。図15は、図14に示すC−C´を通る半導体装置の断面を示す図である。
比較例に係る半導体装置では、図4に示したように、不純物添加領域12と絶縁領域14の間に、半導体領域68が設けられていない。そして、絶縁領域14における第1の領域50及び第2の領域52に電界が集中する。一方、本実施形態に係る半導体装置では、半導体領域68は、ソース電極18の電位よりも高く、ドレインパッド38の電位よりも低い電位に設定される。このため、比較例で第1の領域50に印加された電圧は、半導体領域68の不純物添加領域12に隣接した第4の領域70、及び絶縁領域14の半導体領域68に隣接した第5の領域72の両方に分割されて印加される。
以下に、実施の形態12に係る半導体装置の構成について説明する。図16は、実施の形態12に係る半導体装置の上面図である。
以下に、実施の形態13に係る半導体装置の構成及び効果について、実施の形態12と異なる点のみを説明する。図24は、実施の形態13に係る半導体装置の上面図である。導体46は、ゲート配線32を介して第1のゲート電極86と接続するように設けられている。このため、導体46の電位Vは、ゲート電極16の電位に設定され、実施の形態12の場合より低く設定できる。
12 不純物添加領域
14 絶縁領域
16 ゲート電極
18 ソース電極(第1の電極)
20 ドレイン電極
28 ゲートパッド(第1のパッド)
30 ソースパッド
32 ゲート配線
34、114 ビアホール
38 ドレインパッド
46 導体
48 絶縁膜
64 窪み
66 突出部
68 半導体領域
80 第1のn型トランジスタ(第1の素子)
82 第2のn型トランジスタ(第2の素子)
84 第1の不純物添加領域
86 第1のゲート電極
88 第1のソース電極
90 第1のドレイン電極
92 第1のゲートパッド
94 第1のソースパッド
96 第1のドレインパッド
98 第2の不純物添加領域
100 第2のゲート電極
102 第2のソース電極
104 第2のドレイン電極
106 第2のゲートパッド
108 第2のソースパッド
110 第2のドレインパッド
112 抵抗素子
116 MIMキャパシタ
Claims (13)
- 半導体基板と、
前記半導体基板の上面側に設けられた不純物添加領域と、
前記半導体基板の上面側において、イオン注入によって前記不純物添加領域の周囲に設けられた絶縁領域と、
前記不純物添加領域上に設けられたゲート電極と、
前記ゲート電極を挟むように前記不純物添加領域上に設けられた第1の電極及び第2の電極と、
前記絶縁領域上に設けられ、前記ゲート電極に接続した第1のパッドと、
前記絶縁領域上において前記不純物添加領域を挟んで前記第1のパッドと対向するように設けられ、前記第2の電極に接続した第2のパッドと、
少なくとも一部が前記絶縁領域上の直上において、前記第1の電極と前記第2のパッドの間を結ぶ直線上に設けられた導体と、
を備え、
前記導体は前記不純物添加領域を取囲むことを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板の上面側に設けられた不純物添加領域と、
前記半導体基板の上面側において、イオン注入によって前記不純物添加領域の周囲に設けられた絶縁領域と、
前記不純物添加領域上に設けられたゲート電極と、
前記ゲート電極を挟むように前記不純物添加領域上に設けられた第1の電極及び第2の電極と、
前記絶縁領域上に設けられ、前記ゲート電極に接続した第1のパッドと、
前記絶縁領域上において前記不純物添加領域を挟んで前記第1のパッドと対向するように設けられ、前記第2の電極に接続した第2のパッドと、
少なくとも一部が前記絶縁領域上の直上において、前記第1の電極と前記第2のパッドの間を結ぶ直線上に設けられた導体と、
前記絶縁領域上において、前記不純物添加領域に対して前記第1のパッドが設けられた側と同じ側に設けられ、前記第1の電極に接続した第3のパッドと、
を備え、
前記導体は、前記不純物添加領域、前記第1及び第3のパッドを挟むように、前記不純物添加領域に対して前記第1のパッドが設けられた側と同じ側に開口部を有するU字状に設けられていることを特徴とする半導体装置。 - 前記導体は前記絶縁領域にショットキー接合する金属であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記導体は前記絶縁領域にオーミック接合する金属であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記導体は前記不純物添加領域と同一導電型の半導体であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第2の電極の電位をV2とし、前記ゲート電極と前記第2の電極の間の耐圧をBVg2としたとき、前記導体の電位Vは、(V2−BVg2)≦V≦V2を満たすように設定されていること特徴とする請求項3に記載の半導体装置。
- 前記第1の電極の電位をV1とし、前記第2の電極の電位をV2としたとき、前記導体の電位Vは、V1≦V≦V2を満たすように設定されていることを特徴とする請求項4又は5に記載の半導体装置。
- 前記導体の電位は、前記第1の電極と前記第2のパッドの間の電位差を抵抗分割して得た電位差を、前記第1の電極の電位に加えた電位に設定されていることを特徴とする請求項3〜5のいずれか1項に記載の半導体装置。
- 半導体基板と、
前記半導体基板の上面側に設けられた不純物添加領域と、
前記半導体基板の上面側において、イオン注入によって前記不純物添加領域の周囲に設けられた絶縁領域と、
前記不純物添加領域上に設けられたゲート電極と、
前記ゲート電極を挟むように前記不純物添加領域上に設けられた第1の電極及び第2の電極と、
前記絶縁領域上に設けられ、前記ゲート電極に接続した第1のパッドと、
前記絶縁領域上において前記不純物添加領域を挟んで前記第1のパッドと対向するように設けられ、前記第2の電極に接続した第2のパッドと、
少なくとも一部が前記絶縁領域上の直上において、前記第1の電極と前記第2のパッドの間を結ぶ直線上に設けられた導体と、
を備え、
前記導体は前記絶縁領域にショットキー接合する金属であり、
前記導体は、前記ゲート電極と接続しており、
前記導体及び前記ゲート電極は、前記第1の電極を取囲むようにリング形状に一体形成されたことを特徴とする半導体装置。 - 前記絶縁領域上において、前記導体を覆うように設けられた絶縁膜を更に備え、
前記第1の電極は前記絶縁膜を介して前記導体を覆っていることを特徴とする請求項1〜9のいずれか1項に記載の半導体装置。 - 前記導体は、前記絶縁領域の上面側の窪みに設けられたことを特徴とする請求項1〜10のいずれか1項に記載の半導体装置。
- 前記導体は、前記第2のパッド側又は前記第1の電極側に突出して前記絶縁領域とは離れるように設けられた突出部を有すること特徴とする請求項1〜11のいずれか1項に記載の半導体装置。
- 前記絶縁領域上に絶縁膜を更に備え、
前記導体は前記絶縁膜を介して前記絶縁領域上に設けられていることを特徴とする請求項1〜12のいずれか1項に記載の半導体装置。
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