JP5434360B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5434360B2 JP5434360B2 JP2009190645A JP2009190645A JP5434360B2 JP 5434360 B2 JP5434360 B2 JP 5434360B2 JP 2009190645 A JP2009190645 A JP 2009190645A JP 2009190645 A JP2009190645 A JP 2009190645A JP 5434360 B2 JP5434360 B2 JP 5434360B2
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/794—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/8312—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009190645A JP5434360B2 (ja) | 2009-08-20 | 2009-08-20 | 半導体装置及びその製造方法 |
| CN2010102507775A CN101996874B (zh) | 2009-08-20 | 2010-08-11 | 半导体器件及半导体器件制造方法 |
| US12/854,613 US8896068B2 (en) | 2009-08-20 | 2010-08-11 | Semiconductor device including source/drain regions and a gate electrode, and having contact portions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009190645A JP5434360B2 (ja) | 2009-08-20 | 2009-08-20 | 半導体装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011044517A JP2011044517A (ja) | 2011-03-03 |
| JP2011044517A5 JP2011044517A5 (enExample) | 2012-08-30 |
| JP5434360B2 true JP5434360B2 (ja) | 2014-03-05 |
Family
ID=43604633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009190645A Active JP5434360B2 (ja) | 2009-08-20 | 2009-08-20 | 半導体装置及びその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8896068B2 (enExample) |
| JP (1) | JP5434360B2 (enExample) |
| CN (1) | CN101996874B (enExample) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5003515B2 (ja) | 2007-03-20 | 2012-08-15 | ソニー株式会社 | 半導体装置 |
| KR102524562B1 (ko) * | 2011-12-22 | 2023-04-21 | 인텔 코포레이션 | 반도체 구조 |
| JP2013165224A (ja) * | 2012-02-13 | 2013-08-22 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
| KR101923120B1 (ko) * | 2012-03-21 | 2018-11-28 | 삼성전자 주식회사 | 반도체 소자 및 이의 제조 방법 |
| FR2990295B1 (fr) | 2012-05-04 | 2016-11-25 | St Microelectronics Sa | Procede de formation de contacts de grille, de source et de drain sur un transistor mos |
| US9461143B2 (en) | 2012-09-19 | 2016-10-04 | Intel Corporation | Gate contact structure over active gate and method to fabricate same |
| CN103794507A (zh) * | 2012-11-05 | 2014-05-14 | 中国科学院微电子研究所 | 后栅工艺中器件隔离方法 |
| US8901627B2 (en) * | 2012-11-16 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jog design in integrated circuits |
| US9054172B2 (en) | 2012-12-05 | 2015-06-09 | United Microelectrnics Corp. | Semiconductor structure having contact plug and method of making the same |
| US9153483B2 (en) * | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
| US9136131B2 (en) * | 2013-11-04 | 2015-09-15 | Globalfoundries Inc. | Common fill of gate and source and drain contacts |
| US20150171206A1 (en) * | 2013-12-18 | 2015-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxially Growing III-V Contact Plugs for MOSFETs |
| US9111931B2 (en) * | 2014-01-22 | 2015-08-18 | Nanya Technology Corporation | Method of forming an interconnect structure with high process margins |
| US9431513B2 (en) * | 2014-09-29 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy gate structure and methods thereof |
| US10727122B2 (en) | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
| US10062762B2 (en) * | 2014-12-23 | 2018-08-28 | Stmicroelectronics, Inc. | Semiconductor devices having low contact resistance and low current leakage |
| US9799560B2 (en) * | 2015-03-31 | 2017-10-24 | Qualcomm Incorporated | Self-aligned structure |
| FR3037714A1 (fr) | 2015-06-18 | 2016-12-23 | St Microelectronics Crolles 2 Sas | Procede de realisation d'un contact sur une zone active d'un circuit integre, par exemple realise sur un substrat du type soi, en particulier fdsoi, et circuit integre correspondant |
| TWI658593B (zh) * | 2015-08-10 | 2019-05-01 | 聯華電子股份有限公司 | 半導體裝置及其製作方法 |
| FR3048103B1 (fr) | 2016-02-22 | 2018-03-23 | Stmicroelectronics (Rousset) Sas | Procede de detection d'un amincissement du substrat semi-conducteur d'un circuit integre depuis sa face arriere et circuit integre correspondant |
| KR102493128B1 (ko) * | 2016-04-12 | 2023-01-31 | 삼성디스플레이 주식회사 | 박막트랜지스터 기판, 이를 포함하는 표시 장치 및 그 제조 방법 |
| US10121873B2 (en) * | 2016-07-29 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate and contact plug design and method forming same |
| US10510598B2 (en) | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned spacers and method forming same |
| TWI720077B (zh) | 2016-12-07 | 2021-03-01 | 聯華電子股份有限公司 | 半導體元件的布局 |
| US10062784B1 (en) | 2017-04-20 | 2018-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned gate hard mask and method forming same |
| KR20220129116A (ko) * | 2017-06-23 | 2022-09-22 | 메르크 파텐트 게엠베하 | 선택적 필름 성장을 위한 원자층 증착 방법 |
| US10515896B2 (en) | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
| US10910313B2 (en) * | 2017-11-16 | 2021-02-02 | Samsung Electronics Co., Ltd. | Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch |
| US10867844B2 (en) * | 2018-03-28 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wet cleaning with tunable metal recess for VIA plugs |
| KR102609372B1 (ko) * | 2018-08-31 | 2023-12-06 | 삼성전자주식회사 | 반도체 소자 |
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| US11069784B2 (en) * | 2019-05-17 | 2021-07-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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| US11837640B2 (en) * | 2021-06-29 | 2023-12-05 | Sandisk Technologies Llc | Transistors with stepped contact via structures and methods of forming the same |
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| US6445050B1 (en) * | 2000-02-08 | 2002-09-03 | International Business Machines Corporation | Symmetric device with contacts self aligned to gate |
| JP2001291770A (ja) | 2000-04-11 | 2001-10-19 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
| JP2002190592A (ja) * | 2000-12-22 | 2002-07-05 | Toshiba Microelectronics Corp | 半導体装置及びその製造方法 |
| US6498062B2 (en) * | 2001-04-27 | 2002-12-24 | Micron Technology, Inc. | DRAM access transistor |
| JP2003077936A (ja) * | 2001-09-04 | 2003-03-14 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
| CN100336226C (zh) * | 2001-12-14 | 2007-09-05 | 株式会社日立制作所 | 半导体器件 |
| JP4557508B2 (ja) * | 2003-06-16 | 2010-10-06 | パナソニック株式会社 | 半導体装置 |
| US8003470B2 (en) * | 2005-09-13 | 2011-08-23 | Infineon Technologies Ag | Strained semiconductor device and method of making the same |
| US7416949B1 (en) * | 2007-02-14 | 2008-08-26 | Texas Instruments Incorporated | Fabrication of transistors with a fully silicided gate electrode and channel strain |
| JP2008218727A (ja) * | 2007-03-05 | 2008-09-18 | Renesas Technology Corp | 半導体装置とその製造方法 |
| JP2008288329A (ja) * | 2007-05-16 | 2008-11-27 | Toshiba Corp | 半導体装置 |
| JP2009170857A (ja) * | 2007-09-28 | 2009-07-30 | Elpida Memory Inc | 半導体装置及びその製造方法 |
| KR101026382B1 (ko) * | 2007-12-28 | 2011-04-07 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
| JP2009164391A (ja) * | 2008-01-08 | 2009-07-23 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
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| US8896068B2 (en) | 2014-11-25 |
| US20110042752A1 (en) | 2011-02-24 |
| CN101996874B (zh) | 2012-10-31 |
| JP2011044517A (ja) | 2011-03-03 |
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