JP5426596B2 - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
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- JP5426596B2 JP5426596B2 JP2011066672A JP2011066672A JP5426596B2 JP 5426596 B2 JP5426596 B2 JP 5426596B2 JP 2011066672 A JP2011066672 A JP 2011066672A JP 2011066672 A JP2011066672 A JP 2011066672A JP 5426596 B2 JP5426596 B2 JP 5426596B2
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- 239000004065 semiconductor Substances 0.000 title claims description 64
- 230000015654 memory Effects 0.000 claims description 235
- 230000008859 change Effects 0.000 claims description 108
- 239000000758 substrate Substances 0.000 claims description 18
- 239000003575 carbonaceous material Substances 0.000 claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 289
- 230000014759 maintenance of location Effects 0.000 description 31
- 238000000034 method Methods 0.000 description 21
- 239000000203 mixture Substances 0.000 description 16
- 230000008569 process Effects 0.000 description 14
- 101000575029 Bacillus subtilis (strain 168) 50S ribosomal protein L11 Proteins 0.000 description 12
- 102100035793 CD83 antigen Human genes 0.000 description 12
- 101000946856 Homo sapiens CD83 antigen Proteins 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000012535 impurity Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 239000011159 matrix material Substances 0.000 description 9
- 101150083013 FIN1 gene Proteins 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 101000592939 Bacillus subtilis (strain 168) 50S ribosomal protein L24 Proteins 0.000 description 3
- 101001093025 Geobacillus stearothermophilus 50S ribosomal protein L7/L12 Proteins 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002071 nanotube Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/35—Material including carbon, e.g. graphite, grapheme
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
Description
第1の実施形態にかかる不揮発性半導体記憶装置100について図1を用いて説明する。図1(a)は、不揮発性半導体記憶装置100の概略構成を示す斜視図であり、図1(b)は、不揮発性半導体記憶装置100における上側のメモリセルと下側のメモリセルとを含む部分の等価回路図である。
なお、上側のメモリセルMC211及び下側のメモリセルMC111は、下地膜101上に配されている。
D1<D2<D3
となるように決定した。そして、所定の放置時間を経た後に、各メモリセルアレイについてデータリテンションが良好となるビット(メモリセル)の割合について評価を行った。その結果、抵抗変化層の膜厚がD1→D2→D3と厚くなるに従って、データリテンションが良好となるビットの割合が増加する傾向にあることが確認された。このことから、熱工程の回数の多い下側のメモリセルMC111における抵抗変化層106の膜厚D106を、熱工程の回数の少ない上側のメモリセルMC211における抵抗変化層114の膜厚D114より厚くすることで、上側のメモリセルと下側のメモリセルとの間におけるデータリテンションのばらつきを低減できることが確認できた。
メモリ層MC4におけるメモリセルの抵抗変化層の膜厚<メモリ層MC3におけるメモリセルの抵抗変化層の膜厚<メモリ層MC2におけるメモリセルの抵抗変化層の膜厚<メモリ層MC1におけるメモリセルの抵抗変化層の膜厚
となっていてもよい。
次に、第2の実施形態にかかる不揮発性半導体記憶装置100iについて説明する。以下では、第1の実施形態と異なる点を中心に説明する。
次に、第3の実施形態にかかる不揮発性半導体記憶装置100jについて説明する。以下では、第1の実施形態と異なる点を中心に説明する。
なお、上側のメモリセルMC311j及び下側のメモリセルMC111jは、下地領域172の上に配されている。
CS2=CS1×6
となるように決定した。そして、所定の放置時間を経た後に、各メモリセルアレイについてデータリテンションが良好となるビット(メモリセル)の割合について評価を行った。データリテンションが良好かどうかの基準として、抵抗の変化率が50%以上であることとした。すなわち、図13(b)に示すように、基準ラインより下に分布するビット(メモリセル)をNGとした。その結果、セルサイズがCS1→CS2と大きくなるに従って、データリテンションが良好となるビットの割合が増加する傾向にあることが確認された。このことから、熱工程の回数の多い下側のメモリセルMC111jにおける抵抗変化層177の平面方向の幅を、熱工程の回数の少ない上側のメモリセルMC311jにおける抵抗変化層197の平面方向の幅より広くすることで、上側のメモリセルと下側のメモリセルとの間におけるデータリテンションのばらつきを低減できることが確認できた。
メモリ層MC4におけるメモリセルのセルサイズ<メモリ層MC3におけるメモリセルのセルサイズ<メモリ層MC2におけるメモリセルのセルサイズ<メモリ層MC1におけるメモリセルのセルサイズ
となっていてもよい。
Claims (3)
- 半導体基板と、
前記半導体基板上に配置された第1のラインと、
前記第1のラインの前記半導体基板と反対側に配された第1のメモリセルと、
前記第1のメモリセルを介して前記第1のラインに交差する第2のラインと、
前記第2のラインの前記半導体基板と反対側に配された第2のメモリセルと、
前記第2のメモリセルを介して前記第2のラインに交差する第3のラインと、
を備え、
前記第1のメモリセルは、カーボン系の材料で形成された第1の抵抗変化層と、第1の整流層とを有し、
前記第2のメモリセルは、金属酸化物で形成された第2の抵抗変化層と、第2の整流層とを有し、
前記カーボン系の材料は、SiCを主成分とする第1のカーボン系材料を含む
ことを特徴とする不揮発性半導体記憶装置。 - 前記第1の抵抗変化層の膜厚は、前記第2の抵抗変化層の膜厚より厚い
ことを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記第1の抵抗変化層の前記半導体基板に平行な平面方向の幅は、前記第2の抵抗変化層の前記半導体基板に平行な平面方向の幅より大きい
ことを特徴とする請求項1又は2に記載の不揮発性半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2011066672A JP5426596B2 (ja) | 2011-03-24 | 2011-03-24 | 不揮発性半導体記憶装置 |
US13/422,417 US9053783B2 (en) | 2011-03-24 | 2012-03-16 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
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---|---|---|---|
JP2011066672A JP5426596B2 (ja) | 2011-03-24 | 2011-03-24 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012204542A JP2012204542A (ja) | 2012-10-22 |
JP5426596B2 true JP5426596B2 (ja) | 2014-02-26 |
Family
ID=46876564
Family Applications (1)
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JP2011066672A Expired - Fee Related JP5426596B2 (ja) | 2011-03-24 | 2011-03-24 | 不揮発性半導体記憶装置 |
Country Status (2)
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US (1) | US9053783B2 (ja) |
JP (1) | JP5426596B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014049175A (ja) * | 2012-08-31 | 2014-03-17 | Toshiba Corp | 不揮発性半導体記憶装置、及びそのフォーミング方法 |
US10930705B2 (en) * | 2018-03-28 | 2021-02-23 | International Business Machines Corporation | Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays |
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US7157314B2 (en) * | 1998-11-16 | 2007-01-02 | Sandisk Corporation | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6525953B1 (en) * | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
US6831856B2 (en) * | 2002-09-23 | 2004-12-14 | Ovonyx, Inc. | Method of data storage using only amorphous phase of electrically programmable phase-change memory element |
US7034332B2 (en) * | 2004-01-27 | 2006-04-25 | Hewlett-Packard Development Company, L.P. | Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making |
US7646630B2 (en) * | 2004-11-08 | 2010-01-12 | Ovonyx, Inc. | Programmable matrix array with chalcogenide material |
KR100682899B1 (ko) * | 2004-11-10 | 2007-02-15 | 삼성전자주식회사 | 저항 변화층을 스토리지 노드로 구비하는 메모리 소자의제조 방법 |
US20070132049A1 (en) * | 2005-12-12 | 2007-06-14 | Stipe Barry C | Unipolar resistance random access memory (RRAM) device and vertically stacked architecture |
WO2008023637A1 (fr) * | 2006-08-25 | 2008-02-28 | Panasonic Corporation | Élément de stockage, dispositif mémoire et circuit intégré à semi-conducteur |
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JP5063337B2 (ja) * | 2007-12-27 | 2012-10-31 | 株式会社日立製作所 | 半導体装置 |
JP5113584B2 (ja) * | 2008-03-28 | 2013-01-09 | 株式会社東芝 | 不揮発性記憶装置及びその製造方法 |
EP2107571B1 (en) * | 2008-04-03 | 2012-04-25 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device |
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JP2010062418A (ja) | 2008-09-05 | 2010-03-18 | Toshiba Corp | 不揮発性記憶装置の製造方法 |
JP2010087259A (ja) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | 不揮発性記憶装置の製造方法 |
CN101878530B (zh) * | 2008-10-01 | 2012-03-07 | 松下电器产业株式会社 | 非易失性存储元件和使用该元件的非易失性存储装置 |
KR20100041139A (ko) * | 2008-10-13 | 2010-04-22 | 삼성전자주식회사 | 상변화 물질이 3개 이상의 병렬 구조를 가짐으로써, 하나의메모리 셀에 2비트 이상의 데이터를 저장하는 멀티 레벨 셀 형성방법 |
JP2010135527A (ja) * | 2008-12-04 | 2010-06-17 | Hitachi Ltd | 半導体記憶装置およびその製造方法 |
JP2010219282A (ja) | 2009-03-17 | 2010-09-30 | Toshiba Corp | 不揮発性記憶装置および不揮発性記憶装置の製造方法 |
JP2010225815A (ja) | 2009-03-23 | 2010-10-07 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP5422237B2 (ja) | 2009-03-23 | 2014-02-19 | 株式会社東芝 | 不揮発性記憶装置の製造方法 |
JP2010225741A (ja) * | 2009-03-23 | 2010-10-07 | Toshiba Corp | 不揮発性半導体記憶装置 |
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JP2011014640A (ja) * | 2009-06-30 | 2011-01-20 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011014795A (ja) * | 2009-07-03 | 2011-01-20 | Toshiba Corp | 不揮発性記憶装置 |
JP2011014796A (ja) * | 2009-07-03 | 2011-01-20 | Toshiba Corp | 不揮発性記憶装置 |
JP2012019191A (ja) * | 2010-06-10 | 2012-01-26 | Toshiba Corp | 不揮発性記憶装置の製造方法 |
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US8658997B2 (en) * | 2012-02-14 | 2014-02-25 | Intermolecular, Inc. | Bipolar multistate nonvolatile memory |
-
2011
- 2011-03-24 JP JP2011066672A patent/JP5426596B2/ja not_active Expired - Fee Related
-
2012
- 2012-03-16 US US13/422,417 patent/US9053783B2/en active Active
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US9053783B2 (en) | 2015-06-09 |
JP2012204542A (ja) | 2012-10-22 |
US20120241716A1 (en) | 2012-09-27 |
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