JP5422669B2 - 半導体装置の製造方法、ダイナミックスレッショルドトランジスタの製造方法 - Google Patents
半導体装置の製造方法、ダイナミックスレッショルドトランジスタの製造方法 Download PDFInfo
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- JP5422669B2 JP5422669B2 JP2011543065A JP2011543065A JP5422669B2 JP 5422669 B2 JP5422669 B2 JP 5422669B2 JP 2011543065 A JP2011543065 A JP 2011543065A JP 2011543065 A JP2011543065 A JP 2011543065A JP 5422669 B2 JP5422669 B2 JP 5422669B2
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
以下、図1A〜図1Pを参照しながら、第1の実施形態によるMOSトランジスタの製造方法を説明する。
次に第2の実施形態によるMOSトランジスタの製造工程を、図5A〜図5Sを参照しながら説明する。
図7A〜図7Cは、前記図5Iの工程に引き続き、前記第2の実施形態の一変形例として実行される第3の実施形態による半導体装置の製造工程を示す図である。ただし図8A〜8C中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。また図7Aは図5Iと同じであり説明を省略する。
図9A〜図9Dは、第4の実施形態による半導体装置の製造方法を示す図である。以下の例ではnチャネルMOSトランジスタの製造方法について説明するが、pチャネルMOSトランジスタも同様にして製造することができる。
以上の実施形態では、最初のシリコン基板中にトレンチを形成し、前記トレンチにSiGe混晶層とシリコンエピタキシャル層とをエピタキシャル成長させた後、前記SiGe混晶層を選択エッチングすることにより、半導体装置のソース領域およびドレイン領域の下に絶縁領域を形成していた。
図12は第6の実施形態によるダイナミックスレッショルドMOS(Dt−MOS)トランジスタ70の例を示す。
図16A〜図16Cは、前記図12のDt−MOSトランジスタ70Aを製造する第7の実施形態による製造方法を示す断面図である。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
2,11SG1〜11SG3,31SG1〜31SG4,31SGV1,31SGV2,51SG1,51SG2 SiGe混晶層
3,11ES1〜11ES3,31ES1〜31ES4、51ES1,51ES2 シリコンエピタキシャル層
11A,11B,31A,31B,51A,71A素子領域
11CH1,11CH2,31CH1,31CH2,51CH 基板部分
11I1〜11I3,31I1〜31I3,51I,71I STI型素子分離領域
11IF,31IF,51IF,71Ia〜71Ic 埋込絶縁膜
11NW,31NW,71NW n型ウェル
11PW,31PW,71PW p型ウェル
11TA1〜11TA3,31TA1〜31TA4,51TA,51TB,71TA,71TB トレンチ
11TI1〜11TI3 素子分離溝
11V1〜11V3,31V1〜31V4,51V1,51V2,61V1,61V2,71V ボイド
11a〜11h,31a〜31h,51a〜51d,71a〜71h 拡散領域
12,32,52,72A,72B ゲート絶縁膜
13G1,13G2,33G1,33G2,53G,73A,73B ゲート電極
13GW1,13GW2,33GW1,33GW2,33GW3,33GW4,53GW,73GW サイドウォールスペーサ
13SW1,13SW2,33SW1,33SW2,73GA,74SW 側壁絶縁膜
14S1,14D1,14S2,14D2,14G1,14G2 シリサイド層
15,37,54,74 層間絶縁膜
15A〜15D,37A〜37D ビアホール
16A〜16D,38A〜38D,54A,54B ビアプラグ
17A 圧縮応力膜
17B 引張応力膜
31SCV1,31SCV2, SiC混晶層
34 絶縁膜
51tb,51tc,51td,51te ファセット
53pS,63pS ポリシリコンパタ―ン
53pSG 多結晶SiGeパタ―ン
61DS1,61DS2 Bドープシリコンエピタキシャル層
70A,70B Dt−MOSトランジスタ
71BA p型ボディ領域
73Ga マスクパターン
Claims (10)
- シリコン基板を、チャネル領域が形成されるシリコン基板部分を残してエッチングすることにより、前記シリコン基板部分の第1および第2の側に第1および第2のトレンチをそれぞれ形成する工程と、
前記第1および第2のトレンチ内に、シリコンに対しエッチング選択性を有する半導体層とシリコン層とを順次エピタキシャルに成長することにより、それぞれ形成する工程と、
前記半導体層を、前記シリコン層および前記シリコン基板に対し選択的エッチングにより除去し、前記シリコン基板部分の前記第1および第2の側において、前記シリコン層の下にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、埋込絶縁膜を形成する工程と、
前記シリコン基板部分上にゲート絶縁膜およびゲート電極を形成する工程と、
前記シリコン基板部分の前記第1の側において前記シリコン層中にソース領域を、前記シリコン基板部分の前記第2の側において前記シリコン層中にドレイン領域を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - シリコン基板上に、前記シリコン基板上の素子領域に含まれチャネル領域が形成されるシリコン基板部分をマスクパターンにより覆う工程と、
前記シリコン基板を、前記マスクパターンをマスクとしてエッチングし、前記シリコン基板部分の第1の側および前記第1の側とは反対の第2の側に、それぞれ第1および第2のトレンチを形成する工程と、
前記シリコン基板上に、前記マスクパターンをマスクとして使い、シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシャルに成長することにより、前記第1および第2のトレンチの各々の中に、前記シリコンに対しエッチング選択性を有する半導体層と前記シリコン層とを順次積層した積層構造を形成する工程と、
前記マスクパターンを除去した後、前記シリコン層中に、前記素子領域を画定するように、STI構造の素子分離領域を構成する素子分離溝を、前記素子分離溝が前記シリコンに対しエッチング選択性を有する半導体層を露出するように形成する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を、前記素子分離溝を介して選択的に除去して、前記シリコン基板と前記シリコン層との間にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、前記素子分離溝を介して、埋込絶縁膜を形成する工程と、
前記シリコン基板部分上にゲート絶縁膜を介してゲート電極を形成する工程と、
前記シリコン基板部分中に前記ゲート電極をマスクに、第1の導電型の不純物元素のイオン注入を行い、前記ゲート電極の第1の側に前記第1の導電型のソースエクステンション領域を、前記ゲート電極の、前記第1の側とは反対の第2の側に、前記第1の導電型のドレインエクステンション領域を形成する工程と、
前記ゲート電極の前記第1の側の側壁面と前記第2の側の側壁面にそれぞれの側壁絶縁膜を形成し、前記側壁絶縁膜をマスクに前記第1の導電型の不純物元素のイオン注入を行い、前記第1の側にエピタキシャルに形成された前記シリコン層に前記第1の導電型のソース領域を、また前記第2の側にエピタキシャルに形成された前記シリコン層に前記第1の導電型のドレイン領域を、それぞれ形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記素子分離溝の形成は、前記素子分離溝が、前記シリコンに対しエッチング選択性を有する半導体層の下のシリコン基板に到達するように実行されることを特徴とする請求項2記載の半導体装置の製造方法。
- STI型の素子分離領域により素子領域を画成されたシリコン基板上に、前記素子領域に含まれるシリコン基板部分においてゲート絶縁膜を介してゲート電極を形成する工程と、
前記シリコン基板部分中、前記ゲート電極の第1の側および前記第1の側と反対の第2の側に、第1の導電型の不純物元素を導入することにより、それぞれソースエクステンション領域およびドレインエクステンション領域を形成する工程と、
前記ゲート電極の前記第1の側および前記第2の側の側壁面に、それぞれ側壁絶縁膜を形成する工程と、
前記側壁絶縁膜をマスクに前記シリコン基板をエッチングし、前記ゲート電極の前記第1の側および前記第2の側に、前記ゲート電極から見てそれぞれの側壁絶縁膜の外側において、第1および第2のトレンチをそれぞれ形成する工程と、
前記第1および第2のトレンチの各々の中に、シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシャルに成長することにより、前記シリコンに対しエッチング選択性を有する半導体層と前記シリコン層を順次積層した積層構造を形成する工程と、
前記積層構造を形成する工程の後、前記STI型の素子分離領域を構成する素子分離絶縁膜を後退させ、前記シリコンに対しエッチング選択性を有する半導体層を、前記STI型の素子分離領域を構成する素子分離溝において露出する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を、前記素子分離溝を介して選択的に除去して、前記シリコン基板と前記シリコン層との間にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、前記素子分離溝を介して、埋込絶縁膜を形成する工程と、
前記ゲート電極の前記第1の側および第2の側において、前記積層構造を構成する前記シリコン層中に前記第1の導電型の不純物元素を導入することにより、それぞれソース領域およびドレイン領域を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - STI型の素子分離領域により素子領域を画成されたシリコン基板上に、前記素子領域
に含まれるシリコン基板部分においてゲート絶縁膜を介してゲート電極を形成する工程と、
前記シリコン基板部分中、前記ゲート電極の第1の側および前記第1の側と反対の第2の側に、第1の導電型の不純物元素を導入することにより、それぞれソースエクステンション領域およびドレインエクステンション領域を形成する工程と、
前記ゲート電極の前記第1の側および前記第2の側の側壁面に、それぞれ側壁絶縁膜を形成する工程と、
前記側壁絶縁膜をマスクに前記シリコン基板をエッチングし、前記ゲート電極の前記第1の側および前記第2の側に、前記ゲート電極から見てそれぞれの側壁絶縁膜の外側において、第1および第2のトレンチをそれぞれ形成する工程と、
前記STI型の素子分離領域を構成する素子分離絶縁膜の膜厚を減らす工程と、
前記素子分離絶縁膜の膜厚を減らす工程の後、前記第1および第2のトレンチの各々の中に、シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシャルに成長することにより、前記シリコンに対しエッチング選択性を有する半導体層と前記シリコン層を順次積層した積層構造により、前記シリコンに対しエッチング選択性を有する半導体層が、前記素子分離領域を構成する素子分離溝において露出するように形成する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を、前記素子分離溝を介して選択的に除去して、前記シリコン基板と前記シリコン層との間にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、前記素子分離溝を介して、埋込絶縁膜を形成する工程と、
前記ゲート電極の前記第1の側および第2の側において、前記積層構造を構成する前記シリコン層中に前記第1の導電型の不純物元素を導入することにより、それぞれソース領域およびドレイン領域を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - STI型の素子分離領域により素子領域を画成されたシリコン基板上に、前記素子領域に含まれるシリコン基板部分においてゲート絶縁膜を介してゲート電極を形成する工程と、
前記シリコン基板部分中、前記ゲート電極の第1の側および前記第1の側と反対の第2の側に、第1の導電型の不純物元素を導入することにより、それぞれソースエクステンション領域およびドレインエクステンション領域を形成する工程と、
前記ゲート電極の前記第1の側および前記第2の側の側壁面に、それぞれ側壁絶縁膜を形成する工程と、
前記側壁絶縁膜をマスクに前記シリコン基板をエッチングし、前記ゲート電極の前記第1の側および前記第2の側に、前記ゲート電極から見てそれぞれの側壁絶縁膜の外側において、第1および第2のトレンチをそれぞれ形成する工程と、
前記第1および第2のトレンチの各々の中に、シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシャルに成長することにより、前記シリコンに対しエッチング選択性を有する半導体層と前記シリコン層を順次積層した積層構造を形成する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を露出する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を選択的に除去して、前記シリコン基板と前記シリコン層との間にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、前記素子分離溝を介して、埋込絶縁膜を形成する工程と、
前記ゲート電極の前記第1の側および第2の側において、前記シリコン層中に前記第1の導電型の不純物元素を導入することにより、それぞれソース領域およびドレイン領域を形成する工程と、を含み、
前記シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシ
ャルに成長する工程では、前記シリコンに対しエッチング選択性を有する半導体層とシリコン層とが、それぞれ結晶面よりなるファセットにより画成される斜面を形成し、
前記シリコンに対しエッチング選択性を有する半導体層を露出する工程は、前記シリコン層に対し、前記シリコン基板の主面に垂直方向に作用する異方性エッチングを行い、前記シリコン層のうち、前記ファセットを形成している部分を除去することにより実行されることを特徴とする半導体装置の製造方法。 - 前記シリコンに対しエッチング選択性を有する半導体層はSiGe混晶層であり、前記SiGe混晶層の選択的な除去は、フッ酸と過酸化水素と酢酸を含むエッチャントを使ったウェットエッチング、または塩素を含むエッチングガスを使ったドライエッチングにより実行されることを特徴とする請求項1〜6のうち、いずれか一項記載の半導体装置の製造方法。
- 前記シリコンに対しエッチング選択性を有する半導体層は、ボロンを1×1018cm-3以上の濃度で含むシリコン層であり、前記ボロンを1×1018cm-3以上の濃度で含むシリコン層の選択的な除去は、フッ酸と硝酸と酢酸を含むエッチャントを使ったウェットエッチングにより実行されることを特徴とする請求項1〜6のうち、いずれか一項記載の半導体装置の製造方法。
- 前記埋込絶縁膜を形成する工程の後、前記シリコン層を、前記埋込絶縁膜に対して選択的に除去する工程と、前記埋込絶縁膜上に、シリコンとは異なる格子定数を有する半導体層を、前記シリコン基板部分に対してエピタキシャルに成長させ、歪み領域を形成する工程を含む特徴とする請求項4〜6のうち、いずれか一項記載の半導体装置の製造方法。
- STI型の素子分離領域により素子領域を画成され、前記素子領域の下に第1の導電型の第1ウェルを形成され、前記第1の導電型の前記第1のウェルの上に、前記素子領域に対応して前記第1の導電型とは逆の第2の導電型の第2のウェルを形成されたシリコン基板上への、ダイナミックスレッショルドMOSトランジスタの製造方法であって、
前記素子領域に含まれるシリコン基板部分においてゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート電極をマスクに前記シリコン基板をエッチングし、前記ゲート電極の第1の側および第2の側に第1および第2のトレンチを、前記第1および第2のトレンチが前記第2のウェルに到達するようにそれぞれ形成する工程と、
前記第1および第2のトレンチの各々を、シリコンに対しエッチング選択性を有する半導体層とシリコン層を順次エピタキシャルに成長することにより、前記シリコンに対しエッチング選択性を有する半導体層と前記シリコン層を順次積層した積層構造により形成する工程と、
前記積層構造により形成する工程の後、前記STI型の素子分離領域を構成する素子分離絶縁膜の膜厚を減らし、前記シリコンに対しエッチング選択性を有する半導体層を、前記STI型の素子分離領域を構成する素子分離溝において露出する工程と、
前記シリコンに対しエッチング選択性を有する半導体層を、前記素子分離溝を介して選択的に除去して、前記シリコン基板と前記シリコン層との間にボイドを形成する工程と、
前記ボイド内の少なくとも一部に、前記素子分離溝を介して、埋込絶縁膜を形成する工程と、
前記ゲート電極の前記第1の側および第2の側において、前記積層構造を構成する前記シリコン層中に前記第1の導電型の不純物元素を導入することにより、それぞれソース領域およびドレイン領域を形成する工程と、
前記ゲート電極を前記第2のウェルに電気的に接続する工程と、を含み、
前記第1および第2のトレンチを前記積層構造により充填する工程は、前記シリコンに対しエッチング選択性を有する半導体層を、前記第2のウェルと前記第1のウェルとの接合面を超えて成長させることを特徴とするダイナミックスレッショルドMOSトランジスタの製造方法。
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