JP5419929B2 - 低圧での分子接着接合方法 - Google Patents

低圧での分子接着接合方法 Download PDF

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Publication number
JP5419929B2
JP5419929B2 JP2011146293A JP2011146293A JP5419929B2 JP 5419929 B2 JP5419929 B2 JP 5419929B2 JP 2011146293 A JP2011146293 A JP 2011146293A JP 2011146293 A JP2011146293 A JP 2011146293A JP 5419929 B2 JP5419929 B2 JP 5419929B2
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Japan
Prior art keywords
wafer
wafers
bonding
microcomponents
substrate
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Active
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JP2011146293A
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English (en)
Japanese (ja)
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JP2012039095A (ja
JP2012039095A5 (https=
Inventor
ブロッカール マルセル
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Soitec SA
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Soitec SA
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Publication of JP2012039095A5 publication Critical patent/JP2012039095A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Pressure Welding/Diffusion-Bonding (AREA)
  • Micromachines (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Pressure Sensors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2011146293A 2010-08-11 2011-06-30 低圧での分子接着接合方法 Active JP5419929B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1056566 2010-08-11
FR1056566A FR2963848B1 (fr) 2010-08-11 2010-08-11 Procede de collage par adhesion moleculaire a basse pression

Publications (3)

Publication Number Publication Date
JP2012039095A JP2012039095A (ja) 2012-02-23
JP2012039095A5 JP2012039095A5 (https=) 2013-07-25
JP5419929B2 true JP5419929B2 (ja) 2014-02-19

Family

ID=43617963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011146293A Active JP5419929B2 (ja) 2010-08-11 2011-06-30 低圧での分子接着接合方法

Country Status (7)

Country Link
EP (1) EP2418678B1 (https=)
JP (1) JP5419929B2 (https=)
KR (1) KR101238679B1 (https=)
CN (1) CN102376623B (https=)
FR (2) FR2963848B1 (https=)
SG (1) SG178659A1 (https=)
TW (2) TWI527131B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2978297A1 (fr) * 2011-07-23 2013-01-25 Soitec Silicon On Insulator Reduction d'interferences mecaniques dans un systeme de collage de substrats a basse pression
FR2992772B1 (fr) * 2012-06-28 2014-07-04 Soitec Silicon On Insulator Procede de realisation de structure composite avec collage de type metal/metal
FR2997224B1 (fr) * 2012-10-18 2015-12-04 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire
WO2016101992A1 (de) 2014-12-23 2016-06-30 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zur vorfixierung von substraten
EP3417477B1 (de) * 2016-02-16 2020-01-29 EV Group E. Thallner GmbH Verfahren zum bonden von substraten
FR3079532B1 (fr) * 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
CN110767589B (zh) * 2019-10-31 2021-11-19 长春长光圆辰微电子技术有限公司 一种soi硅片对准键合的方法
CN112635362B (zh) * 2020-12-17 2023-12-22 武汉新芯集成电路制造有限公司 晶圆键合方法及晶圆键合系统

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3720515B2 (ja) * 1997-03-13 2005-11-30 キヤノン株式会社 基板処理装置及びその方法並びに基板の製造方法
EP0886306A1 (en) * 1997-06-16 1998-12-23 IMEC vzw Low temperature adhesion bonding method for composite substrates
EP1052687B1 (en) * 1998-02-02 2016-06-29 Nippon Steel & Sumitomo Metal Corporation Method for manufacturing an soi substrate.
US6008113A (en) * 1998-05-19 1999-12-28 Kavlico Corporation Process for wafer bonding in a vacuum
JP2000199883A (ja) * 1998-10-29 2000-07-18 Fujitsu Ltd 反射型プロジェクタ装置
US6958255B2 (en) * 2002-08-08 2005-10-25 The Board Of Trustees Of The Leland Stanford Junior University Micromachined ultrasonic transducers and method of fabrication
EP1815500A2 (en) * 2004-10-09 2007-08-08 Applied Microengineering Limited Equipment for wafer bonding
JP2009094164A (ja) * 2007-10-04 2009-04-30 Toshiba Corp インバータ装置における電力用半導体素子
JP5354900B2 (ja) * 2007-12-28 2013-11-27 株式会社半導体エネルギー研究所 半導体基板の作製方法
FR2931014B1 (fr) * 2008-05-06 2010-09-03 Soitec Silicon On Insulator Procede d'assemblage de plaques par adhesion moleculaire
JP2010021326A (ja) * 2008-07-10 2010-01-28 Sumco Corp 貼り合わせウェーハの製造方法
FR2935537B1 (fr) * 2008-08-28 2010-10-22 Soitec Silicon On Insulator Procede d'initiation d'adhesion moleculaire
EP2200077B1 (en) * 2008-12-22 2012-12-05 Soitec Method for bonding two substrates
JP5668275B2 (ja) * 2009-04-08 2015-02-12 株式会社Sumco Ｓｏｉウェーハの製造方法及び貼り合わせ装置

Also Published As

Publication number Publication date
TWI527131B (zh) 2016-03-21
FR2963848B1 (fr) 2012-08-31
CN102376623A (zh) 2012-03-14
TW201214583A (en) 2012-04-01
KR20120015266A (ko) 2012-02-21
TW201428859A (zh) 2014-07-16
FR2963848A1 (fr) 2012-02-17
EP2418678A2 (en) 2012-02-15
SG178659A1 (en) 2012-03-29
KR101238679B1 (ko) 2013-03-04
FR2969378A1 (fr) 2012-06-22
CN102376623B (zh) 2014-07-02
EP2418678A3 (en) 2012-02-29
EP2418678B1 (en) 2014-10-15
JP2012039095A (ja) 2012-02-23

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