JP5419929B2 - 低圧での分子接着接合方法 - Google Patents
低圧での分子接着接合方法 Download PDFInfo
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- 230000010070 molecular adhesion Effects 0.000 claims description 25
- 230000000977 initiatory effect Effects 0.000 claims description 18
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- 238000004519 manufacturing process Methods 0.000 claims description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
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- 239000000356 contaminant Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Micromachines (AREA)
- Lining Or Joining Of Plastics Or The Like (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Pressure Sensors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
スペーサ要素のうちの1つを後退させるステップと、
2つのウエハに対して、2つのウエハを互いに対して位置合せするように、プッシャによって第1の横方向力を加えるステップであって、ウエハが少なくとも1つの保持フィンガによって保持されている、ステップと、
他のスペーサ要素を後退させるステップと、
プッシャを後退させるステップと、
2つのウエハに対してプッシャによって第2の横方向力を加えるステップと、
プッシャを後退させるステップと
を含む。
第1の一連のマイクロコンポーネントと第2の一連のマイクロコンポーネントとの間の残留位置合せずれが、本構造の表面全体にわたって均一に100nm未満である、3次元複合構造に関する。
21 切欠き
22 上面
30 ウエハ
31 切欠き
32 下面
40 基板保持装置
40a 支持板
41、42、43 スペーサ要素
44 プッシャ
441 ヘッド
45、46 保持フィンガ
50 ツール
51 スタイレット
52 端部
52a 接触面積
53 動力計
100 接合装置
100 初期基板
100a 層
110 チャンバ
110 マイクロコンポーネント
120 基板保持装置
120a 支持板
130 基板保持装置
130a 支持板
200 最終基板
300 複合構造
Pm 機械的圧力
400 3次元構造
410 初期基板
411〜419 マイクロコンポーネント
420 最終基板
421〜429 マイクロコンポーネント
Claims (8)
- 少なくとも第1のウエハ(20)と第2のウエハ(30)との間を分子接着接合する方法であって、少なくとも機械的位置合せのステップと、前記2つのウエハ(20、30)を接触させるステップと、前記2つのウエハの間の接合波の伝播を開始するステップと、を含む、方法において、
機械的位置合せの前記ステップ及び前記2つのウエハを接触させる前記ステップの間、前記ウエハが、所定圧力閾値以上の第1の圧力(P1)の接合装置のチャンバ内に配置され、
接合波の伝播を開始する前記ステップの間、前記ウエハ(20、30)が、前記接合波を自発的に開始するように、前記所定圧力閾値未満かつ1ミリバール未満の第2の圧力(P2)の前記接合装置の前記チャンバ内に配置され、
前記2つのウエハは、少なくとも前記2つのウエハを接触させる前記ステップの始めから接合波の伝播を開始する前記ステップの終わりまでの間、前記接合装置の前記チャンバ内に配置され、
前記所定の圧力閾値が20ミリバール以下5ミリバール以上であることを特徴とする方法。 - 前記機械的位置合せ及び前記2つのウエハ(20、30)を接触させる前記ステップの前に、前記2つのウエハの間の空間を維持するように前記2つのウエハの間に少なくとも3つのスペーサ要素(41、42、43)を介在させると同時に、前記ウエハが互いに面するように配置され、前記機械的位置合せ及び前記2つのウエハ(20、30)を接触させる前記ステップが、
前記スペーサ要素のうちの1つ(41)を後退させるステップと、
前記2つのウエハ(20、30)に対して、前記2つのウエハを互いに対して位置合せするように、プッシャ(44)によって第1の横方向力を加えるステップであって、前記ウエハが少なくとも1つの保持フィンガ(45;46)によって保持されている、ステップと、
他のスペーサ要素(42、43)を後退させるステップと、
前記プッシャ(44)を後退させるステップと、
前記2つのウエハ(20、30)に対して前記プッシャ(44)によって第2の横方向力を加えるステップと、
前記プッシャ(44)を後退させるステップと
を含むことを特徴とする、請求項1に記載の方法。 - 第1のウエハ(100)の第1の面(101)の上に第1の一連のマイクロコンポーネント(110)を製作するステップと、少なくとも機械的位置合せのステップ、及び前記第1の一連のマイクロコンポーネントを備えた前記第1のウエハ(100)の前記第1の面を第2のウエハ(200)の面と接触させるステップとを含み、その後に、前記2つのウエハ(100、200)の間の接合波の伝播を開始するステップが続く、3次元複合構造(300)を製造する方法において、機械的位置合せの前記ステップ、前記ウエハを接触させる前記ステップ、及び前記ウエハの間の接合波の伝播を開始する前記ステップが、請求項1又は2に記載の接合方法に従って行われることを特徴とする方法。
- 前記接合ステップの後、前記第1のウエハ(100)を薄層化して層(100a)を形成するステップを含むことを特徴とする、請求項3に記載の方法。
- 前記層(100a)の、前記第1の一連のマイクロコンポーネント(110)を備えた前記面と反対側の面(102)に、第2の一連のマイクロコンポーネント(140)を製作するステップをさらに含むことを特徴とする、請求項4に記載の方法。
- 前記接合するステップの前に、前記第1の基板(100)の前記第1の一連のマイクロコンポーネント(110)を備えた前記面の上に、酸化物層を形成するステップを含むことを特徴とする、請求項3〜5のいずれか一項に記載の方法。
- 前記第1の基板(100)がSOI型の構造であることを特徴とする、請求項3〜6のいずれか一項に記載の方法。
- 少なくとも前記第1の一連のマイクロコンポーネント(110)がイメージセンサを備えることを特徴とする、請求項3〜7のいずれか一項に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1056566A FR2963848B1 (fr) | 2010-08-11 | 2010-08-11 | Procede de collage par adhesion moleculaire a basse pression |
FR1056566 | 2010-08-11 |
Publications (3)
Publication Number | Publication Date |
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JP2012039095A JP2012039095A (ja) | 2012-02-23 |
JP2012039095A5 JP2012039095A5 (ja) | 2013-07-25 |
JP5419929B2 true JP5419929B2 (ja) | 2014-02-19 |
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JP2011146293A Active JP5419929B2 (ja) | 2010-08-11 | 2011-06-30 | 低圧での分子接着接合方法 |
Country Status (7)
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EP (1) | EP2418678B1 (ja) |
JP (1) | JP5419929B2 (ja) |
KR (1) | KR101238679B1 (ja) |
CN (1) | CN102376623B (ja) |
FR (2) | FR2963848B1 (ja) |
SG (1) | SG178659A1 (ja) |
TW (2) | TWI527131B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2978297A1 (fr) * | 2011-07-23 | 2013-01-25 | Soitec Silicon On Insulator | Reduction d'interferences mecaniques dans un systeme de collage de substrats a basse pression |
FR2992772B1 (fr) | 2012-06-28 | 2014-07-04 | Soitec Silicon On Insulator | Procede de realisation de structure composite avec collage de type metal/metal |
FR2997224B1 (fr) * | 2012-10-18 | 2015-12-04 | Soitec Silicon On Insulator | Procede de collage par adhesion moleculaire |
SG11201704557PA (en) * | 2014-12-23 | 2017-07-28 | Ev Group E Thallner Gmbh | Method and device for prefixing substrates |
SG11201805655VA (en) | 2016-02-16 | 2018-07-30 | Ev Group E Thallner Gmbh | Method and device for bonding substrates |
FR3079532B1 (fr) * | 2018-03-28 | 2022-03-25 | Soitec Silicon On Insulator | Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain |
CN110767589B (zh) * | 2019-10-31 | 2021-11-19 | 长春长光圆辰微电子技术有限公司 | 一种soi硅片对准键合的方法 |
CN112635362B (zh) * | 2020-12-17 | 2023-12-22 | 武汉新芯集成电路制造有限公司 | 晶圆键合方法及晶圆键合系统 |
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JP3720515B2 (ja) * | 1997-03-13 | 2005-11-30 | キヤノン株式会社 | 基板処理装置及びその方法並びに基板の製造方法 |
EP0886306A1 (en) * | 1997-06-16 | 1998-12-23 | IMEC vzw | Low temperature adhesion bonding method for composite substrates |
KR100565438B1 (ko) * | 1998-02-02 | 2006-03-30 | 신닛뽄세이테쯔 카부시키카이샤 | Soi기판 및 그의 제조방법 |
US6008113A (en) * | 1998-05-19 | 1999-12-28 | Kavlico Corporation | Process for wafer bonding in a vacuum |
JP2000199883A (ja) * | 1998-10-29 | 2000-07-18 | Fujitsu Ltd | 反射型プロジェクタ装置 |
US6958255B2 (en) * | 2002-08-08 | 2005-10-25 | The Board Of Trustees Of The Leland Stanford Junior University | Micromachined ultrasonic transducers and method of fabrication |
EP1815500A2 (en) * | 2004-10-09 | 2007-08-08 | Applied Microengineering Limited | Equipment for wafer bonding |
JP2009094164A (ja) * | 2007-10-04 | 2009-04-30 | Toshiba Corp | インバータ装置における電力用半導体素子 |
JP5354900B2 (ja) * | 2007-12-28 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
FR2931014B1 (fr) * | 2008-05-06 | 2010-09-03 | Soitec Silicon On Insulator | Procede d'assemblage de plaques par adhesion moleculaire |
JP2010021326A (ja) * | 2008-07-10 | 2010-01-28 | Sumco Corp | 貼り合わせウェーハの製造方法 |
FR2935537B1 (fr) * | 2008-08-28 | 2010-10-22 | Soitec Silicon On Insulator | Procede d'initiation d'adhesion moleculaire |
EP2200077B1 (en) * | 2008-12-22 | 2012-12-05 | Soitec | Method for bonding two substrates |
JP5668275B2 (ja) * | 2009-04-08 | 2015-02-12 | 株式会社Sumco | Soiウェーハの製造方法及び貼り合わせ装置 |
-
2010
- 2010-08-11 FR FR1056566A patent/FR2963848B1/fr not_active Expired - Fee Related
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2011
- 2011-06-29 TW TW100122921A patent/TWI527131B/zh active
- 2011-06-29 TW TW103113917A patent/TW201428859A/zh unknown
- 2011-06-30 JP JP2011146293A patent/JP5419929B2/ja active Active
- 2011-07-01 SG SG2011048584A patent/SG178659A1/en unknown
- 2011-07-12 EP EP11173513.0A patent/EP2418678B1/en active Active
- 2011-08-02 KR KR1020110076876A patent/KR101238679B1/ko active IP Right Grant
- 2011-08-09 CN CN201110229518.9A patent/CN102376623B/zh active Active
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2012
- 2012-01-24 FR FR1250663A patent/FR2969378A1/fr active Pending
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Publication number | Publication date |
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CN102376623A (zh) | 2012-03-14 |
TW201214583A (en) | 2012-04-01 |
SG178659A1 (en) | 2012-03-29 |
EP2418678B1 (en) | 2014-10-15 |
CN102376623B (zh) | 2014-07-02 |
FR2963848A1 (fr) | 2012-02-17 |
EP2418678A2 (en) | 2012-02-15 |
TW201428859A (zh) | 2014-07-16 |
FR2963848B1 (fr) | 2012-08-31 |
JP2012039095A (ja) | 2012-02-23 |
TWI527131B (zh) | 2016-03-21 |
KR101238679B1 (ko) | 2013-03-04 |
FR2969378A1 (fr) | 2012-06-22 |
KR20120015266A (ko) | 2012-02-21 |
EP2418678A3 (en) | 2012-02-29 |
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