JP5404689B2 - 半導体素子、及び半導体素子製造方法 - Google Patents
半導体素子、及び半導体素子製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 36
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 46
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- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 11
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 10
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- 238000001312 dry etching Methods 0.000 claims description 7
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 5
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Description
光子源は、単一の動作中の量子ドットを有する単一光子源であってもよいし、複数の光子を出力するように構成されていてもよい。そのような光子源は複数の量子ドットを有する。
第1の層を形成し、
前記第1の層の上に覆い被さるストレッサー層を形成し、前記ストレッサー層は前記第1の層に対して本質的に異なる格子定数を有して、
さらなる層を形成し、パターン層を形成するために前記さらなる層に少なくとも1つのピットの模様をつけ、前記ピットは、量子ドットを形成することが望ましい位置に位置し、
m層以下の単原子層を具備するドット層を形成し、前記ドット層は、自己組織化した量子ドットを、上に覆い被さってかつ接触する層上に形成することができる材料を具備し、ここでmは5であり、量子ドットを前記ピットに形成される。
Claims (19)
- 量子構造及び複数の層を具備する半導体素子であって、前記複数の層は、第1の層と、ストレッサー層と、及び、パターン層と、を具備し、前記ストレッサー層は前記第1の層の上に覆い被さり、前記パターン層は前記ストレッサー層の上に覆い被さり、前記ストレッサー層は前記第1の層の格子定数とは3から8%だけ異なる格子定数を有して、前記素子は、少なくとも前記パターン層に提供されるピットをさらに具備し、前記量子構造は前記ピットで提供され、前記ピットの最下段と前記ストレッサー層との距離がスペーサ層の厚みよりも小さい半導体素子。
- 前記構造は量子ドットである請求項1の半導体素子。
- 前記パターン層は、複数のピットと、前記ピットと協調する複数の量子構造と、を具備する請求項1または請求項2の半導体素子。
- 複数の量子ドット層をさらに具備し、前記量子構造は成長の方向に整列している請求項1から請求項3のいずれか1項の半導体素子。
- 前記ストレッサー層は、少なくとも1nmの厚みを有する請求項1から請求項4のいずれか1項の半導体素子。
- 前記第1の層はGaAsを具備し、前記ストレッサー層はIn(x)Ga(1−x)Asを具備し、量子ドットはIn(y)Ga(1−y)As InAsを具備し、InGaAsストレッサー層でのIn濃度はx=0.2−1の範囲である請求項1から請求項5のいずれか1項の半導体素子。
- 前記ストレッサー層、前記パターン層、及び前記構造は、電気的コンタクトを提供するドープされた半導体層の間にある請求項1から請求項6のいずれか1項の半導体素子。
- 前記ピットは、横方向の大きさが300nmより小さく、深さが5nmから100nmである請求項1から請求項7のいずれか1項の半導体素子。
- 前記パターン層の上に覆い被さり接触する再生バッファー層をさらに具備する請求項1から請求項8のいずれか1項の半導体素子。
- 前記再生バッファー層は、100nm未満である厚さを有する請求項9の半導体素子。
- 前記ピットはパターン層を介してストレッサー層に及ぶまで延長する請求項1から請求項10のいずれか1項の半導体素子。
- 光子源として構成され、前記量子構造は量子ドットであり、前記素子は、p型ドープ層が量子ドットの一面に提供され、n型ドープ層が量子ドットの他面に提供されるp−i−n構造を具備し、前記素子は、前記n及びp型層への電気的コンタクトと、場が前記量子ドットに印加されるように前記コンタクトに接続する源と、をさらに具備する請求項1から請求項11のいずれか1項の半導体素子。
- 光キャビティをさらに具備し、前記キャビティは、前記層の平面に垂直な方法で光閉じ込めを提供し、前記ピットは前記キャビティ内の波腹で提供される請求項12の半導体素子。
- 前記キャビティは、光結晶欠陥キャビティである請求項13の半導体素子。
- 検出器として構成され、前記量子構造は量子ドットであり、前記素子は、p型ドープ層が量子ドットの一面に提供され、n型ドープ層が量子ドットの他面に提供されるp−i−n構造を具備し、前記素子は、前記n及びp型層への電気的コンタクトと、電流が測定されるように前記コンタクトに接続される測定部と、をさらに具備する請求項1から請求項12のいずれか1項の半導体素子。
- レジスターとして構成され、前記量子構造は量子ドットであり、複数のゲートをさらに具備し、各ゲートはドットの列の上に覆い被さって提供され、ドットの列は成長方向に整列された複数のドットによって提供される請求項3の半導体素子。
- 半導体素子で量子ドットを位置決めする方法であって、
第1の層を形成し、
前記第1の層の上に覆い被さるストレッサー層を形成し、前記ストレッサー層は前記第1の層の格子定数とは3から8%だけ異なる格子定数を有していて、
さらなる層を形成し、パターン層を形成するために前記さらなる層に少なくとも1つのピットの模様をつけ、前記ピットは量子ドットを形成することが望ましい位置に位置し、
m層以下の単原子層を具備するドット層を形成し、前記ドット層は、自己組織化した量子ドットを、上に覆い被さってかつ接触する層上に形成することができる材料を具備し、ここでInAs/GaAsシステムに関してmは1.6から1.7であり、前記量子ドット層は量子ドットを前記ピットに形成し、前記ピットの最下段と前記ストレッサー層との距離がスペーサ層の厚みよりも小さい方法。 - 前記模様をつけることは、ドライエッチング技術を使用して行われる請求項17の方法。
- 前記量子ドットの形成後にさらなるパターンを前記ピットと並べること、前記ピットと並べられた前記さらなるパターンをエッチングすることをさらに具備する請求項17または請求項18の方法。
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JP6296548B2 (ja) * | 2014-07-02 | 2018-03-20 | 富士通株式会社 | 光子発生装置及び光子発生方法 |
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GB2531568B (en) * | 2014-10-22 | 2018-07-04 | Toshiba Res Europe Limited | An optical device and method of fabricating an optical device |
GB2549703B (en) * | 2016-04-19 | 2019-11-06 | Toshiba Kk | An optical device and method for its fabrication |
US10593756B2 (en) * | 2016-08-12 | 2020-03-17 | Intel Corporation | Quantum dot array devices |
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GB201007802D0 (en) | 2010-06-23 |
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