WO2006017220A1

WO2006017220A1 - Process to grow a highly ordered quantum dot array, quantum dot array grown in accordance with the process, and devices incorporating same

Info

Publication number: WO2006017220A1
Application number: PCT/US2005/024527
Authority: WO
Inventors: Jingming Xu; Jianyu Liang; Roderic. J. Beresford
Original assignee: Brown University
Priority date: 2004-07-13
Filing date: 2005-07-11
Publication date: 2006-02-16

Abstract

A method to fabricate an array of quantum dots (18) includes etching an array of holes (10A) into a surface of a substrate (10) through apertures in a mask (12); removing the mask (12); and epitaxially depositing a first semiconductor material into individual ones of the holes (10A) to form the array of quantum dots (18). In a non-limiting embodiment of the invention the substrate (10) is a GaAs substrate that is reactive ion etched to form an array of holes (10A) through apertures (12A) in a mask (12) made from an anodic aluminum (AAO)) membrane (12). A buffer layer of GaAs may be deposited by molecular beam epitaxy at least within individual ones of the holes (10A), and InAs is deposited by molecular beams epitaxy over the buffer layer in individual ones of the holes (10A) to form the array of quantum dots (18). Devices that incorporate the array of quantum dots (18) are also described.

Description

PROCESS TO GROW A HIGHLY ORDERED QUANTUM DOT ARRAY,

QUANTUM DOT ARRAY GROWN IN ACCORDANCE WITH THE

PROCESS, AND DEVICES INCORPORATING SAME

TECHNICAL FIELD:

This invention relates generally to growth techniques employed with semiconductor materials and, more specifically, relates to the growth of ordered arrays of microscopic structures (nano-structures) of semiconductor material having desirable electrical and/or optical properties, such as an array of quantum dots.

BACKGROUND:

As an analog for an artificial atom, the semiconductor quantum dot is attracting intensive research attention that aims to characterize the interplay of crystal morphology (e.g., size, shape, strain, cladding) with the quantum dynamics of the interaction with an optical field. The growth of quantum dots by self-assembly mechanisms, based on the control and balance of strain-mismatch conditions, has been achieved. Such advances have enabled the development of a new generation of electronic and optoelectronic devices, and have also facilitated the study of bio-molecular systems and fundamentally interesting quantum phenomena.

General reference with regard to the foregoing can be made to the following publications: D. Gammon, Nature 405, 899-900 (2000); W. E. Buhro, V. L. Colvin, Nature Materials 2, 138 - 139 (2003); L. Landin, M. S. Miller, M.-E. Pistol, C. E. Pryor, L. Samuelson, Science 280, 262-264 (1998); R. P. Mirin, A. C. Gossard, in Quantum Semiconductor Devices and Technologies, T.P. Pearsall, Ed. (Kluwer Academic Publishers, 2000), pp. 183-231; R. Nόtzel et al., Nature 392, 56-59 (1998); T. Ishikawa, T. Nishimura, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 76, 167 (2000); and T. Ishikawa, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 73, 1712 (1998).

However, despite these advances what has been lacking to date is an effective technique to synthesize three dimensional (3D) confined nano-structures that also possess a high degree of spatial ordering, that is, uniformity not just of size and shape, but also of the spatial relationship between the nano-structures (also referred to for convenience as "dots", as in quantum dots). What is recognized as a desirable goal is a periodic superstructure of uniform quantum dots. For many applications, it is also desirable to provide the quantum dots in a densely packed form.

To date, quantum dot growth by self-assembly has been constrained to a few material compositions and size ranges in which the critical strain-mismatch conditions can be met. It would thus be a further desirable goal to provide a wider range of choices in quantum dot composition.

These goals, however desirable, are unlikely to be attainable in the present self-assembling growth regime because of the absence of a feedback mechanism that would allow the self-assembled quantum dots to self-organize into a highly ordered array.

hi order to effectively realize the desired zero-dimensional behavior of a quantum dot ensemble, what is required is an ability to fabricate quantum dot heterostructures with high packing density that also exhibit size and shape uniformity. Both self-assembled growth mechanisms and growth on patterned substrates have been studied previously (see again: R. P. Mirin, A. C. Gossard, in Quantum Semiconductor Devices and Technologies, T.P. Pearsall, Ed. (Kluwer Academic Publishers, 2000), pp. 183-231; R. Nδtzel et al., Nature 392, 56-59 (1998); T. Ishikawa, T. Nishimura, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 76, 167 (2000); and T. Ishikawa, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 73, 1712 (1998)). The Stranski-Kranstanov (SK) growth mode has been demonstrated to provide densely distributed quantum dot ensembles via self-assembly with good crystal quality. However, this approach typically exhibits a limited control over the size distribution, and a lesser control over the spatial position of the dots (see again: R. P. Mirin, A. C. Gossard, in Quantum Semiconductor Devices and Technologies, T.P. Pearsall, Ed. (Kluwer Academic Publishers, 2000), pp. 183-231; and R. Nδtzel et al., Nature 392, 56-59 (1998)). Quantum dots have also been grown on electron-beam lithographically patterned and etched GaAs (see again: T. Ishikawa, T. Nishimura, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 76, 167 (2000); and T. Ishikawa, S. Kohmoto, K. Asakawa, Appl. Phys. Lett. 73, 1712 (1998)). This latter growth method is restricted by the in situ lithography process, and it has not been demonstrated to produce quantum dots with high optical quality.

Based on the foregoing discussion, it should be appreciated that in order to realize the desired zero-dimensional behavior of a quantum dot ensemble, an ability to fabricate quantum dots with a high packing density and an improved size and shape uniformity is important. Prior to this invention, this need was not adequately fulfilled.

SUMMARY OF THE INVENTION

The foregoing and other problems are overcome, and other advantages are realized, in accordance with the embodiments of this invention.

Disclosed herein in accordance with exemplary and non-limiting embodiments of this invention is a highly-ordered Group III-V nano-dot array that is epitaxially grown on a Group III-V substrate of non-lithographically nano-patterned material. In one non- limiting embodiment that is illustrative of certain presently preferred embodiments of this invention the nano-dot array is comprised of hiAs (Indium Arsenide), the substrate is comprised of GaAs (Gallium Arsenide), and the array is grown by a molecular beam epitaxy (MBE) process.

A method to fabricate an array of quantum dots includes etching an array of holes into a surface of a substrate through apertures in a mask; removing the mask; and epitaxially depositing a first semiconductor material into individual ones of the holes to form individual ones of quantum dots, hi a non-limiting embodiment of the invention the substrate is a GaAs substrate that is reactive ion etched to form an array of holes through apertures in a mask made from an anodic aluminum oxide (AAO) membrane. A buffer layer of GaAs is deposited by molecular beam epitaxy at least within individual ones of the holes, and InAs is deposited by molecular beams epitaxy over the buffer layer in individual ones of the holes to form the array of quantum dots. In the exemplary embodiments of quantum dot synthesis there is provided a mechanism to direct and confine the growth of quantum dots on a nano-cavity array that is imprinted into a substrate surface via a highly ordered nano-pore array template, which is itself formed and self-organized in the AAO membrane.

In an illustrative embodiment approximately 20 billion nano-dots are grown in a 1-cm² area with a size nonuniformity of less than 10%, and forming a lateral superlattice in a hexagonal dense packing form. The nano-dot growth techniques in accordance with the preferred embodiments of this invention presage a pathway to three dimensional (3D) periodic superlattices of 3D confined nano-structures, which beneficially offer macroscopic spatial coherence in the interaction of quantum dots with radiation.

A further aspect of this invention relates to a device that comprises an array of quantum dots, where each of the quantum dots comprises a substantially crystalline body comprised of a semiconductor material that is substantially contained within a hole etched into a surface of a substrate. In non-limiting embodiments of the invention the device may be embodied as an emitter of electromagnetic radiation, as a detector of electromagnetic radiation, as an amplifier of electromagnetic radiation or as a logic element.

A further embodiment of a method to fabricate an array of quantum dots has steps that include forming an array of holes in a surface of a substrate through apertures in a mask; epitaxially depositing a first semiconductor material into individual ones of the holes to form individual ones of the quantum dots and removing the mask.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other aspects of these teachings are made more evident in the following Detailed Description of the Preferred Embodiments, when read in conjunction with the attached Drawing Figures, wherein: Figs. IA and IB, collectively referred to as Fig. 1, depict Fast Fourier transform (FFT) images comparing quantum dots fabricated by different methods;

Fig.2 shows enlarged images that facilitate a discussion of quantum dot array fabrication details;

Figs. 3A and 3B, collectively referred to as Fig. 3, illustrate nano-structural details of a quantum dot fabricated in accordance with the invention;

Fig. 4A is an enlarged side cut-away view of a substrate being patterned through a mask during the formation of the quantum dot array in accordance with the embodiments of this invention, and Figs. 4B and 4C show further steps in the quantum dot array fabrication process;

Fig. 5 is an enlarged cross-sectional and simplified view of a laser device that is constructed so as to include a quantum dot array that is fabricated in accordance with the embodiments of this invention;

Fig. 6 is an enlarged cross-sectional and simplified view of a register device that is constructed so as to include a quantum dot array that is fabricated in accordance with the embodiments of this invention;

Fig. 7 is an enlarged cross-sectional and simplified view of a photodetector device that is constructed so as to include a quantum dot array that is fabricated in accordance with the embodiments of this invention;

Fig. 8 is an enlarged cross-sectional view of the array of quantum dots fabricated in accordance with an alternative embodiment of the invention that leaves the mask in place during deposition of buffer layer material, quantum dot material and, optionally, capping layer material;

Fig. 9A shows that an etched substrate will exhibit pore rims and bottom edges with discontinuities in the surface stress tensor that are sources of the bulk elastic strain field, while Fig. 9B shows that a thin coherently strained InAs film that follows the nanopore topography has a biaxial compressive stress that can be relaxed in the regions of the pore rims;

Fig. 9C shows a result of atomic force microscopy measurements of the surface topography of as-etched GaAs nanopores , while Fig. 9D shows the nanopores after 10 min. of thermal cleaning at 580 °C, where the pore depth decreases from about 40 to about 5 nm;

Fig. 9E shows InAs quantum dots grown at 370 °C on a BCl₃-etched GaAs substrate, where the lateral distribution is well defined by the GaAs matrix, resulting in a dot density of about 1.2x10¹⁰ cm^"2;

Fig. 9F illustrates the surface topography of quantum dots grown at 370 °C on a BCl₃- etched GaAs substrate, where the average dot height is about 30 nm above the flat region;

Figs. 9G and H show InAs growths on SiO₂ pre-coated and CF₄-etched GaAs substrates: 11 ML 2D-equivalent dose at 0.3 ML/s (Fig. 9G) and 34 ML dose at 0.17 ML/s (Fig.9H), where the fraction of filled pores increases in proportion to the total InAs dose, while the maximum dot size is approximately constant;

Fig. 91 is a graph that summarizes SEM observations of the fraction of filled pores, plotted versus the total hiAs dose expressed as 2D-equivalent monolayers, where the solid line is the expected slope based on 70-nm dot height and ideal hexagonal close packing of 60-nm diameter dots on 100-nm centers; and

Figs. 9 J and K show TEM cross section of GaAs capped dot ((Fig. 9J) showing a region of detailed analysis (Fig. 9K) indicated by the rectangle, where the X component of the displacement field in the detail region is calculated by phase imaging, using the lattice of the dot material as the reference for zero displacement (where the gray scale covers a dynamic range of 0.15 monolayers). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A nonlimiting aspect of this invention is the directed growth by molecular beam epitaxy (MBE) of highly ordered InAs quantum dot arrays on a GaAs substrate. Scanning electron micrograph (SEM) images of the resulting densely-packed 2D periodic dot arrays vividly reveal a high degree of ordering and uniformity, together with hexagonal dense packing, as shown in Fig. 1.

More specifically, Fig. 1 shows Fast Fourier transform (FFT) images comparing quantum dots fabricated by different methods. For clarity of detail in presentation, negative images are used (the highest intensities in these images are the darkest regions). The ordered InAs quantum dot array (Fig. IA) clearly exhibits a hexagonal diffraction pattern, in contrast to a typical self-assembled InAs quantum dot array (Fig. IB), with only a diffuse band of intensity and no discernible periodicities, hi order to eliminate edge effects the real-space images (the inset images in Figs. IA and IB) are multiplied by a raised cosine window. Scale bars in both inset images are 500 nm.

The internal atomic structure of the quantum dot was found to be very good, as confirmed via x-ray diffraction (XRD) and high-resolution transmission electron microscopy (TEM). Also, an intense and narrowband optical emission associated with the quantum dot array demonstrates material function commensurate with the highly ordered and uniform structure.

Although these results indicate a crystalline lattice of hiAs dots that is mostly or substantially relaxed (adopting the equilibrium lattice parameter of hiAs), a particular feature of the method in accordance with exemplary embodiments of this invention is that it can equally well be adapted to the growth of substantially strained quantum dot material, where the quantum dots adopt the lattice parameter of the substrate, and to the growth of partially relaxed dots, that is, to the controlled production of desired amounts of strain in the quantum dots. The features of this method that enable this degree of control include the fabrication of different dimensions of nano-pores, different total amounts of deposited quantum dot material, and different capping layers, as described in further detail below.

The fabrication techniques in accordance with the embodiments of this invention provide a pathway to 3D periodic superlattices of 3D confined nano-structures, which thus provide for macroscopic spatial coherence in the interaction of quantum dots with electromagnetic radiation.

hi contrast to the conventional quantum dot growth processes discussed above, the directed-growth method in accordance with embodiments of this invention combine a non-lithographic pattern transfer (that can be scaled to large areas) with selective nucleation of SK islands, thus combining high dot density, high crystal quality, size uniformity, and spatial periodicity. As a non-limiting example, approximately 10⁹ dots are grown in a 1-cm² area with a size nonuniformity of less than about 10%, and with a significant degree of long-range positional and orientational order. The resulting array of dots forms a lateral superlattice in a hexagonal dense packing format.

Referring to Fig. 4A, in order to enable directed growth, which in this case comprises area-selective nucleation of SK islands, a substrate 10, such as a GaAs substrate, is patterned by etching, preferably by reactive ion etching (RIE), using (preferably) an anodic aluminum oxide (AAO) membrane as a mask 12. The mask 12 is characterized by having an array of through-holes or apertures 12A. This approach combines a self-organizing process in the anodization of the aluminum film of the AAO membrane, and enhanced self-assembly during MBE growth by patterning. Hexagonally organized nano-pore arrays formed during anodization of aluminum have been observed and reported (see: R. W. Franklin, Nature 187, 1470 (1957); and F. Keller, M. S. Hunter, D. L. Robinson, J. Electochem. Soc. 100, 411 (1953)). Masuda et al. (H. Masuda, K. Fukuda, Science 268, 1466 (1995)) reported the occurrence of defect-free large domains, while defects were found at the boundaries of these domains, after a long anodization period under certain anodizing conditions. Hexagonally ordered nano-pore arrays with periodicities from 50 nm to 420 nm have also been demonstrated (see: A. P. Li, F. Muller, A. Birner, K. Nielsch, U. Gosele, J. Appl. Phys., 84, 6023 (1998)), which correspond to packing densities in the range of approximately 10⁹ cm^'2 to approximately 10^{1 J} cm^"2. Since these reports, efforts have focused on applications of these self-organized nano-pore arrays, such as using them as templates for fabricating a variety of nano- stractures (see: J. Liang, H. Chik, J.M. Xu, IEEE J. SeI. Top. Quant. 8, 998 (2002); and C. R. Martin, Science 266, 1961(1994)).

It is noted that in general it is preferred that the substrate 10 be crystalline. As such, other substrate materials that meet this criterion may also be employed, such as sapphire.

Any suitable technique may be employed to obtain the mask 12 having nano-pore sizes, numbers and spacings in accordance with desired parameters for the resulting array of quantum dots, and the disclosures of at least these various publications that refer to the construction of AAO membranes are incorporated by reference herein as being examples of suitable technique to obtain the mask 12. Reference in this regard can also be made to: F. Li, L. Zhang, R. Metzger, Chem. Mater., 10, 2470-2480 (1998), "On the Growth of Highly Ordered Pores in Anodized Aluminum Oxide", incorporated by reference; and to J. Liang, H. Chik, A. Yin, J.M. Xu, J. Appl. Phys., Vol. 91, No. 4, 15 February 2002, 2544-2546, "Two-dimensional lateral superlattices of nanostructures: Nonlithographic formation by anodic membrane template", incorporated by reference.

Fig. 2 also shows fabrication process details, and illustrates a scanning electron microscope image of a hexagonally ordered hiAs quantum dot array 18 with a periodicity of 110 nm and a diameter of 60 nm in the nano-patterned GaAs substrate 10. The inset image shows the nano-pore array formed in the anodic aluminum oxide membrane or mask 12. The pattern transfer of the nano-pore array of the mask 12 to the GaAs substrate 10 is accomplished by the RIE of the GaAs, as was shown in cross-section in Fig. 4A.

More specifically, in non-limiting embodiments of this invention a nano-pore array pattern is transferred to the GaAs (001) substrate 10 by RIE using BCl₃ as an etchant through the apertures 12A in the mask 12 formed in the AAO membrane. The BCl₃ gas flow rate was 20 seem, and the pressure and power used for the RIE were 15 mTorr and 100 W, respectively. The inset image in Fig. 2 presents a SEM top view image of a typical self-organized nano-hole array in an AAO membrane, in this case having a periodicity of 110 nm and a pore diameter of 60 nm. The AAO membrane was used as the RIE mask 12 to obtain a corresponding array of holes or pores or nano-pores 1OA in the GaAs substrate 10. Certain of the inventors have previously confirmed that the periodicity and the diameter of the etched nano-pores 1 OA in GaAs are determined by the original nano-hole array in the AAO membrane (see J. Liang, H. Chik, A. Yin, J. M. Xu, J. Appl. Phys., 91, 2544 (2002). The depth of the resulting nano-pores 1OA in the GaAs substrate 10 is controlled by controlling the RIE duration. Following the RIE step, the AAO membrane is removed, preferably chemically, leaving the nano-patterned GaAs substrate 10 as shown in Fig. 4B. m general, the holes formed in the substrate 10, that is the nano-pores 1 OA, when using the self-assembled AAO mask 12 may be considered to have a periodicity of about 100 nm, where each hole (nano-pore 10A) has a diameter of less than about 70 nm.

Referring to Fig. 4C, the growth of hiAs quantum dots 16 on the patterned GaAs substrate 10 was conducted by solid-source MBE using As₄ and elemental group III sources. Immediately before being loaded into the MBE system, the nano-patterned GaAs substrate 10 was treated by ultrasonic cleaning in deionized water. A standard thermal cleaning step was performed at 600⁰C with an As beam equivalent pressure of about 1.5 X 10^"5 torr in order to desorb the surface oxide. An As-stable 2X4 reconstructed surface was observed by reflection high-energy electron diffraction (RHEED) to confirm the thermal cleaning effectiveness. All samples were grown under As-rich conditions. About ten monolayers (MLs) of GaAs are first deposited at 580 ⁰C at a growth rate of 1 ML/s, forming a thin GaAs layer 14. It is well known to those versed in GaAs MBE that growth under these conditions will establish or reestablish a smooth surface following oxide desorption (see: A. Y. Cho, Thin SolidFilms 100, 291(1983)). The reason for growing the thin layer 14 of GaAs is to supply a buffer layer that partially fills in the etched topography, in order to avoid growth of the InAs directly on an ion-bombarded surface (as the substrate 10 surface is after the RIE process). Control of the thermal cleaning and buffer layer processes is preferred to prevent the complete obliteration of the etched nano- pore 1OA topography, while yet still providing a high-quality starting surface for the quantum dot growth. Before lowering the substrate temperature to 490⁰C and starting the InAs growth, the samples are maintained at 580⁰C for 10 minutes under As overpressure. After the InAs growth, the samples are annealed for another 10 min. in the MBE chamber at the growth temperature.

In order to achieve the optimal result of confining one and only one InAs quantum dot 16 within each nano-pore 1OA in the GaAs substrate 10, the total amount of InAs and the growth rate are preferably varied according to the variation of etched depth, diameter, and periodicity of the nano-pores 1OA in the GaAs substrate 10. As a general rule, it maybe desired to provide an InAs growth process that would produce dots of similar density and size as would be encountered in a conventional self-assembled SK growth process. However, since not all combinations of dot size and periodicity are accessible in conventional self-assembling growth, this general rule provides only a starting point.

For a first non-limiting and exemplary example discussed here in the XRD and optical measurements, an amount of InAs equivalent to 35 MLs of planar growth was deposited at a rate of 0.05 ML/s on the array of nano-pores 1OA having a periodicity of 110 nm, a nano-pore diameter of 55 nm, and a RIE etching time of 15 min.

For a second non-limiting and exemplary example that provided a sample used for TEM measurements, a similar amount of InAs was deposited at a rate of 0.2 ML/s on a similar GaAs nano-patterned substrate 10.

The formation of the InAs quantum dots 16, exhibiting a relative insensitivity to different MBE growth rates, implies that the nano-pattern imposes an important influence on the growth kinetics and offers an advantage of easily controlling the size, shape, position, and density of the quantum dots 16 by controlling the nano-pattern properties. On the other hand, it is also possible to obtain continuous InAs films due to coalescence of neighboring dots or pore blocking, as well as incompletely filled pores.

Fig. 2 and the inset image in Fig. 3 A display SEM top view and oblique view images of an InAs quantum dot array 18 grown by the foregoing techniques. More specifically, Fig. 3 illustrates nano-structural details of the quantum dot 16, where Fig. 3 A, shows powder X-ray diffraction patterns of the InAs quantum dots 16 on GaAs, and where the inset image shows a SEM oblique view image of the sample (scale bar is 100 nm). Fig. 3B shows a cross-sectional transmission electron microscope image of a single InAs quantum dot grown 16 within a single nano-pore 1 OA in the GaAs substrate 10 (scale bar shows 10 nm).

It is clear that each nano-pore 1 OA in the substrate 10 defines an individual InAs dot 16. The size distribution of the LxAs quantum dots 16, as measured by the standard deviation of the diameter, is about 9% of the mean diameter, which is about 55 nm. The uniformity and long-range order of the array 18 of quantum dots 16 can be analyzed by a two dimensional (2D) Fast Fourier Transform (FFT) of the SEM top view image as shown in Fig. IA and its inset. The FFT clearly demonstrates the hexagonal reciprocal lattice; the small size and high intensity of the diffraction spots are measures of the size uniformity and the spatial ordering of the InAs quantum dots 16. For comparison, an AFM image (and its FFT) of a typical self-assembled InAs quantum dot sample on a planar substrate grown under similar conditions are given in Fig. IB and its inset. The transform in this case shows only a tendency towards a preferred size, as indicated by a fairly broad annular band, and little discernible long-range order. These results stand in marked contrast to the lattice-like image of the ordered-array 18 sample fabricated in accordance with the preferred embodiments of this invention.

The as-grown highly-ordered InAs quantum dots 16 are found to be substantially crystalline, as indicated in the powder XRD pattern (Fig. 3A), matching the bulk InAs peaks for InAs (002) and (004), and in the cross-sectional TEM image of an individual InAs quantum dot 16 (see Fig. 3B). The Moire fringes clearly seen in the TEM image suggest that the in-plane lattice parameter of the hiAs quantum dot 16 has relaxed from the fully strained condition and thus interferes with diffraction from the GaAs substrate 10. Following the observation that GaAs grown at 580 ⁰C smoothes out the starting topography (see again: A. Y. Cho, Thin Solid Films 100, 291(1983)), one may expect that the initial 10 monolayers of GaAs grows preferentially within the nano-pores 1OA and provides an improved starting surface for the InAs quantum dots 16. Observation of samples with a low InAs total dose suggests that the quantum dots 16 most likely nucleate preferentially along the rims of the nano-pores 1OA, as will be discussed in further detail below.

While an exact compositional profile of the InAs Quantum dots 16 was not quantified, experience with self-assembled quantum dots suggests that interdiffusion of Ga and In is to be expected, at least in the near-interfacial region.

Photoluminescence (PL) spectra from a single-layer highly-ordered InAs quantum dot array 18 sample on a nano-patterned GaAs substrate were measured at different temperatures. While the spectral features vary in details with the optical pumping conditions (power, incident angle, wavelength, spot location), principal differences were readily observable when compared with conventional self-organized InAs quantum dots grown on a planar substrate under the same conditions. The narrow PL linewidth, despite the averaging over a large number of dots, confirms the expected small degree of inhomogeneous broadening.

In general, the substrate 10 fabrication maybe done separately, as in the semiconductor industry where often specialist companies provide starting wafers to others that fabricate device structures. Similarly, the AAO membrane 12 maybe created separately from the quantum dot arrays. The growth chamber is optimized for the epitaxy process, whereas other equipment is optimized for the other functions. As for processing compatibility, there are implicitly certain involved issues. For example, and regarding the substrate 10, the issues are the same as for any other conventional epitaxy process, i.e., the substrate 10 should be thermally and chemically stable under the epitaxy conditions. Regarding the mask 12, the issues are the same as for other RIE processes, i.e., the mask 12 should be capable of withstanding the etch chemistry while protecting the underlying substrate material, and be readily removable after the process.

It should be noted that there need be no processing step required for the removal of InAs after the deposition of the InAs into the holes 1OA, as a feature of this type of growth is that due to the lattice mismatch between InAs and GaAs, the InAs.tends to spontaneously aggregate into dots. The patterning (i.e., the formation of the arrays of holes 10A) provides locations that are especially likely for the dots to begin growing. While there may expected to be approximately 1.7 monolayers of InAs (a so-called 'wetting layer') remaining on the GaAs substrate 10 regions between holes 1 OA, this wetting layer would generally not need to be removed as it is too thin to interfere in the device structure.

It should be appreciated that the superior spatial ordering of the directed-growth InAs quantum dots 16 in accordance with the embodiments of this invention are attractive for development of improved devices based on the quantum dots 16. For example, the production of uniform quantum dots has been problematic using conventional techniques. The conventional techniques yield an array of quantum dots of various sizes, thereby limiting their use in, for example lasers, as some quantum dots emit radiation while others absorb, with the net result of little or no lasing activity. Providing a uniform and repeatable spacing has also been problematic using the conventional techniques. The preferred embodiments of this invention overcome these and other problems and provide a uniform quantum dot array 18 that exhibits a defined repeatable spacing.

There are several other evident advantages of the improved array 12 of quantum dots 16 described herein. A first additional advantage relates to the combination of the inherent self-organizational process in the anodization of aluminum and the enhanced self-assembly during epitaxial (MBE) growth. A second additional advantage relates to the facilitated control of quantum dot size, spacing, density, height, and shape by controlling the properties of the AAO membranes and the parameters of the RIE process. A third additional advantage relates to the ability to retain the long-range hexagonal ordering of the quantum dots. A fourth additional advantage relates to the applicability to different material systems (other than GaAs/InAs and more generally Group III-V material systems). A fifth additional advantage relates to the scalability of the process to larger wafers as they become available. When one combines these and other advantages with the capability to adjust the material content in each quantum dot 16 by varying the MBE growth conditions, one is provided with a new pathway for growing highly uniform and ordered quantum dots and an array 18 thereof, as well as with a new dimension of freedom in the design and implementation of devices with new functionalities based on the highly ordered and uniform array 18 of quantum dots 16. The teachings in accordance with the embodiments of this invention can be used to create a number of useful devices, including as non-limiting examples lasers, optical amplifiers and photodetectors.

For the case of the laser, and referring to Fig. 5 that shows an enlarged cross-sectional and simplified view of a laser device 50 that is constructed so as to include a quantum dot array 18 that is fabricated in accordance with the embodiments of this invention. The laser device 50 includes a semiconductor optical gain medium 52 that comprises at least one distribution (array 18) of highly ordered quantum dots, a cavity 54 is disposed in relation to the optical gain medium 52 so as to provide optical feedback, and means to provide electrical or optical pumping to the gain medium 52 such that a population inversion is established and maintained. The population inversion should be adequate to overcome the optical and other losses in the structure and thereby provide pulsed or continuous optical output at an energy determined by the properties of the highly ordered array 18 of quantum dots 16. The cavity 54 may be defined by a pair of opposed distributed Bragg reflectors (DBRs) 54A, 54B.

Reference with regard to a prior quantum dot vertical cavity surface emitting laser (VCSEL) can be had to US 2002/0176474 Al (11/28/2002) by Huang etal. (incorporated by reference herein), which employs one or more conventionally formed layers of QDs grown by a self-assembly process. In accordance with an aspect of this invention the one or more layers of conventional QDs are replaced by one or more of the highly ordered quantum dot arrays 18.

As a further example, the highly ordered array 18 of quantum dots 16 may be employed in constructing logic elements, such as those useful for quantum computing. Reference in this regard may be made, for example, to A. Balandin, G. Jin and K.L. Wang, J. Electronic Materials, 29, 549-553 (2000), "Issues of Practical Realization of a Quantum Dot Register for Quantum Computing". Fig. 6 herein is similar in some respects to Figure 1 of the Balandin et al. publication and shows the use of exactly positioned quantum dots 16 fabricated in accordance with embodiments of this invention, in combination with a layer of control oxide 62 and overlying gates 64, disposed between source and drain regions 66, 68 for forming a quantum dot register 60. Confined electron levels are used to form a qubit. Logic elements other than registers may also be realized using the array 18 of quantum dots 16.

Fig. 7 is an enlarged cross-sectional and simplified view of a photodetector device 70 that is constructed so as to include at least one quantum dot array 18 that is fabricated in accordance with the embodiments of this invention. The photodetector device 70 includes multiple layers of semiconductor material, including one or more layers that incorporate the array 18 of highly ordered quantum dots 16. The one or more arrays 18 of highly ordered quantum dots 16 are preferably sandwiched between barrier layers 76, such that the quantum dots 16 possess energy levels below the level of the barrier layers 76, and contain charge carriers that can be excited by incident electromagnetic radiation, causing an electrical current to flow between device terminals 72, 74.

Reference with regard to a prior quantum dot photodetector, one that is designed to detect infrared (IR) radiation, can be had to US 6,239,449 Bl (05/29/2001) by Fafard et al. (incorporated by reference herein), which employs one or more conventionally formed layers of QDs grown by a self-assembly process. In accordance with an aspect of this invention the one or more layers of conventional QDs are replaced by one or more of the highly ordered quantum dot arrays 18.

A scanned or staring-type image sensor may also be constructed using the array or arrays 18 of highly ordered quantum dots 16 in accordance with the non-limiting embodiments of this invention.

As an additional non-limiting embodiment an optical amplifier may provide for directing an optical signal, such as via a semiconductor optical waveguide, into a semiconductor gain medium that includes a distribution (array 18) of highly ordered quantum dots 16. hi this case the array 18 of highly ordered quantum dots provides gain to the optical signal at an energy up to the emission energy of the array of quantum dots.

In some of the foregoing non-limiting examples it is preferred, for example, that the active area of one light emitter or one pixel of a light sensor contain a plurality of the quantum dots 16 that are electrically contacted in parallel.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best method and apparatus presently contemplated by the inventors for carrying out the invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims.

As but some examples, the use of other similar, equivalent or different semiconductor materials (including possibly other III-V materials such as hiGaN/GaN-based materials and ϊnGaAs/rnP-based materials; silicon-based or germanium-based SiGe/Si or SiGeC/Si materials; or Group II- VI materials systems), mask types and mask pattern dimensions, etching procedures and etchants (such as etchants selected based on the characteristics of the semiconductor material that forms the substrate 10), and different epitaxial growth processes may be attempted by those skilled in the art. In particular, other etching procedures that may be employed in accordance with embodiments of this invention may include other chemistries such as fluorine-based chemistries, alternative plasma-etching configurations such as electron-cyclotron resonance (ECR) plasma or inductively-coupled plasma (ICP) etching, and other combinations of chemical and physical etching mechanisms such as chemically assisted ion beam etching, ion beam etching, and ion milling as applied to semiconductor materials systems such as those listed above. Furthermore, various epitaxial growth procedures such as metalorganic chemical vapor deposition (MOCVD), metalorganic molecular beam epitaxy (MOMBE), reactive sputtering, hydride vapor-phase epitaxy (HVPE), chemical beam epitaxy (CBE), or physical vapor deposition (PVD) may be employed as an alternative to MBE in order to achieve the directed growth of ordered QD arrays on the patterned surfaces, as well as subsequent layers of various semiconductor materials.

As another example, it is within the scope of the teachings of this invention to passivate the semiconductor material surface with a layer of oxide or other insulating material prior to the assembly of the membrane template or mask 12 and the etching steps. Subsequently, during the etching process the passivation layer is removed from the pore regions, thereby protecting sensitive areas of the semiconductor surface during processing.

As a further example, it is within the scope of the teachings of this invention to apply a "capping" or "cladding" layer to the exposed portions of the quantum dots 16. For example, and referring to Fig. 4D, following the deposition of the quantum dot material (e.g., the InAs) one or more additional semiconductor "capping" or "cladding" layers 20 are deposited so as to fully encapsulate the quantum dot material in another material of different composition, e.g., such as by the use of GaAs capping layers to encapsulate any exposed portions of the InAs quantum dots 16. Benefits realized by the use of the capping layer 20 include an improvement in, and control over, the quantum dot properties by protecting the otherwise exposed surface of the quantum dot 16. It is also possible to influence properties of the quantum dot 16 by the presence of lattice mismatch stresses imposed by the material of the capping layer 20. The capping layer 20 may comprise a single layer of semiconductor material, or it may comprise a multi-layered system that comprises semiconductor material or materials.

One or more of the GaAs substrate 10 and capping layers 20 maybe conductive and may form contacts to the quantum dots 16. Conventional GaAs dopants maybe employed to provide the desired type(s) of conductivity, such as Si for n-type and Be or C for p-type conductivity.

The capping layer(s) 20 are preferably grown immediately after the quantum dots 16, and the growth temperature may be adjusted as desired and thus may effectively anneal the material/interface in situ.

In accordance with a still further exemplary embodiment of this invention, and referring to Fig. 8, in some instances it maybe desirable to apply the mask 12 to the surface of the substrate 10, form the nano-pore array through the apertures 12A in the mask, and then deposit the buffer 14 and the dot 16 material into the nano-pores 1OA through the apertures 12A in the mask 12. In this case one may also then, if desired, deposit the capping layer 20 material through the mask 12 apertures, thereby creating a plurality of capping layers 2OA, each associated with one underlying quantum dot 16. The mask 12 is then removed, and at the same time any material that was deposited on the upper surface of the mask 12 can be lifted-off. This exemplary embodiment thus provides an essentially self-aligned growth process, m this case, and as in shown in Fig. 8, the buffer layer 14 and capping layer 20 materials extend to the limits of the etched holes or pores 1 OA, as all three layers of buffer 14, quantum dot 16 and cap 20 are defined by the same mask edge.

It is further noted that the highly-ordered growth behavior of InAs dots 16 on a GaAs substrate 10 may be beneficially enhanced by the use of apre-coated SiO₂ film. The SiO₂ film, which influences the quality of the growth surface and the growth selectivity, is patterned using the nanopore array of the AAO as a mask 12. Analysis of high-resolution TEM images shows that the highly ordered InAs dots 16 are fully relaxed. Different growth temperatures and growth rates maybe used to optimize selectivity of the quantum dot growth sites on the patterned surface.

As was discussed above, and to further reiterate, the size of the quantum dots 16 can be controlled by the growth time and the pore size and depth, ranging from a few monolayers to several tens of monolayers. The dot density is well controlled by the AAO pore spacing, which can vary from 50 nm to 420 nm (A. P. Li, F. Muller, A. Birner, K. Nielsch, and U. Gosele, J. Appl. Phys., 84, 6023 (1998). hi addition to providing highly ordered arrays of dots, the pattern-assisted growth has a range of control over dot parameters that is potentially much larger than that for the self-assembled method. Also, there is the possibility for forming quantum dots with a wider range of materials systems.

The preferred embodiments of this invention employ surface curvature (that is, imposed patterning and etching) to control the position of quantum dot formation. After etching and thermal cleaning at a temperature of 580 °C, the GaAs surface is evidently not in equilibrium, because a smoother surface is recovered after some minutes of annealing under As₄ pressure. The following suggests how the pattern-assisted growth of InAs/GaAs occurs. As is shown in Fig. 9A, the pore rims and bottom edges, idealized as sharp boundaries, are locations of discontinuities in the surface stress tensor and therefore sources of an elastic strain field in the crystal. For a stressed crystal in contact with vacuum, the normal velocity for a surface element may be expressed as:

where the "constant" B can depend on stress or composition, S is the elastic compliance tensor, σ is the stress tensor, f is the excess surface free energy and K! the average curvature of the surface at the element in question in the reference state. The surface stress tensor in principle may be included in Equation (1) as well, but is neglected here for simplicity of illustration.

Equation (1) indicates that local maxima in the elastic energy density and the curvature will tend to degrade as surface atoms are transported by diffusion and attach at local minima of the energy density and the curvature. Observation of the smoothing of the GaAs surface at the oxide desorption temperature illustrate this process, as the regions of negative curvature in the pore bottoms grow by surface in-diffusion of material from the regions of the pore rims, where the curvature is positive and decreasing. By limiting the high-temperature exposure, the nonequilibrium patterned surface can be maintained during deposition of an InAs wetting layer and subsequent nucleation of hiAs dots 16, which appear to selectively populate regions near and inside the pore openings. As suggested in Fig. 9B, a thin coherently (and compressively) strained InAs film that follows the nanopore topography will have regions of stress relaxation at the pore rims and stress concentration at the pore bottom edges. Equation (1) again applies, but in this case the first term in the elastic energy density can have a local minimum at the pore rims due to the relaxation of misfit stress. Hence, the relaxed regions grow in preference to the other regions, the pores fill in starting from the nuclei on the rims, and the dots eventually may extend above the flat surface between the periodically arrayed pores.

As was discussed above, in order to achieve the pattern-driven growth mechanism in accordance with exemplary embodiments of the invention the GaAs (100) substrate 10 is patterned by RIE using the AAO membrane as the etching mask 12. Highly-ordered hexagonal nanopore arrays are formed during anodization of aluminum under controlled conditions. The nanopore array is then transferred onto the GaAs surface during the etching process. Although the diameter of the nanopores can vary from 30 nm to 420 nm depending on the anodization conditions, for a given sample the standard deviation of the pore diameter and spacing is extremely small, typically ~ 5 - 7%. One may use, for convenience, a 60 nm diameter and alOO nm center-to-center spacing. The epi-ready GaAs wafer (substrate) 10 is bonded with the AAO membrane by surface adhesion and then etched under a BCl₃ plasma. The GaAs wafer (substrate) 10 may be etched at the rate of 10 nm/min. with the BCl₃ gas flow of 20 seem, etching pressure of 15 mTorr and rfpower of200 W.

hi the process further in accordance with non-limiting embodiments of this invention, the GaAs wafer is first coated with a thin (e.g., about 50-nm) SiO₂ layer deposited by plasma- enhanced chemical vapor deposition (PECVD). After bonding the AAO membrane, the pores are etched using a CF₄ plasma at the rate of 10 nm/min. in SiO₂ and 2 nm/min. in GaAs, with the CF₄ gas flow set to 20 seem and O₂ flow at 4 seem. The hexagonal array of nanopores is transferred to the GaAs wafer (substrate) 10 after the etching process, hi both processes, the nanopore arrays in the substrate retain the same dimensions of the mask 12, and have a depth of about 40 nm as confirmed by SEM cross-section views. Note that the entire SiO₂ layer is removed due to the isotropic behavior of the F-based etchant. Immediately prior to loading, the sample is cleaned for 10 min in deionized water with ultrasonic agitation.

On the pre-patterned substrate 10 the InAs quantum dots 16 are grown by molecular beam epitaxy (e.g., Veeco Applied EPI 930 MBE). Prior to the growth process, the native oxide layer is desorbed at 580 °C (pyrometer reading) and As₄ pressure of 9xlO^"7 Torr. It was observed that the high-temperature thermal cleaning causes surface diffusion that tends to flatten the nanopore pattern gradually. Samples with different thermal cleaning times are measured by AFM in the non-contact mode. Figs. 9C and 9D compare a sample before any thermal cleaning (Fig. 9C) with one after 10 min. of thermal cleaning (Fig. 9D). The pore depth decreases from 40 nm to 5 nm during the 10 min. exposure, hi order to preserve the nanostructured surface as much as possible, it is desirable to begin the GaAs buffer layer 14 growth immediately after a streaky 2x4 As-stable reconstruction appears in the reflection high energy electron diffraction (RHEED) pattern. Some benefit in terms of reduced thermal exposure may also be achieved by removing the native oxide layer in HF prior to loading the sample. To use this technique, it was found that a hydrophobic GaAs surface is obtained more reliably if the sample is cleaned in an O₂ plasma under conditions of 60 seem gas flow and 200 mTorr pressure before the HF treatment. Following the thermal clean, a 10-monolayer GaAs buffer layer is grown at the rate of 1 ML/s, as may be calibrated by RHEED oscillations. To study the pattern- driven growth mechanism, the InAs quantum dots may be grown at different substrate temperatures and growth rates, hi addition, the 50-nm GaAs capping layer 20 may be grown. The capping layer 20 can be grown at the same temperature as the InAs quantum dots 16, e.g., at a temperature that varies from approximately 480 °C down to approximately 370 °C.

From SEM images of dot 16 morphology, one may can conclude that under arsenic-rich growth conditions the In flux and As₄ pressure have relatively little effect on the pattern- driven growth, whereas the growth temperature plays an important role in the growth mechanism. InAs deposition rates were varied from 0.05 to 0.3 ML/s, and As₄ background pressure from 5 x 1 QT⁷ to 1.5 x 10^"6 Torr. At lower growth temperatures, more of the nanopores are filled by the InAs dots. Typically, at higher growth temperature, larger hiAs dots form on the surface randomly, that is, without obvious correlation to the pattern. The appearance of larger dots at higher temperature in general suggests that dot size is kinetically limited, increasing as the adatom mobility increases. It is found that a temperature of approximately 350 ⁰C is the lower limit for InAs to crystallize on the substrate 10. Fig. 9E shows that InAs quantum dots 16 grown at approximately 370 ⁰C are well confined in the GaAs matrix of the substrate 10, and each quantum dot 16 has a generally pyramidal shape that is the typical hiAs quantum dot crystal structure. The lateral distribution of the dots 16 is well defined by the GaAs matrix of the substrate 10, in this case resulting in a dot density of about 1.2x10¹⁰ cm^"2.

It is noted that the size uniformity is well controlled in the growth, as shown in Fig. 9F, where the average dot height is about 30 nm above the flat region. Results with various InAs growth times reveal a self-limiting aspect to the growth mechanism. At the beginning of the growth, InAs nuclei appear at the rims of the pores randomly and then continue to grow from those locations. After a particular volume is attained, the dot growth slows or stops, and new nuclei are found, which then continue to grow. As a function of InAs exposure, the number of filled pores increases linearly. As shown in Figs. 9G and 9H, a shorter growth time gives fewer pores that are fully filled, but the size of the dots in the filled pores in both cases is about the same. The graph in Fig. 91 shows the relation of the percentage of filled pores vs. the InAs exposure.

The two RIE processes discussed also influence the quantum dot growth. Although the pre-coated SiO₂ layer is etched away completely, the GaAs samples etched in CF₄ have a higher temperature tolerance than those etched in BCl₃, the CF₄-etched nanopores can be well-filled with quantum dots at 480 °C, whereas the BCl₃ samples require a significantly lower temperature of about 430 °C. It maybe reasonably assumed that the protective SiO₂ layer preserves a smoother surface between pores. Since the surface curvature is the basis of the pattern-driven growth, increased roughness is expected to degrade the selectivity. Thus, the SiO₂/CF₄ process appears to operate to improve the contrast between the flat surfaces between the pores and the intentionally curved surface at the pore rims. It is noted that there may be a role played by the presence of residual SiO₂ in enhancing selectivity by nucleating the dots on a surface that has a measurable SiO₂ thickness remaining on the flat regions.

In self-assembled InAs quantum dot growth, it is possible to obtain coherent dots or dislocated (relaxed) dots, depending on the growth conditions. In the processes discussed herein, the InAs dots appear to be relaxed. A first indication of this condition comes from high-resolution TEM images (Fig. 9J), which shows interference contrast as would be expected if material of a different lattice parameter lies beneath the dot region. The second indication, also from the TEM image, is the presence of dislocations in the GaAs cap layer 20, which are expected if the dot material is relaxed. The third indication comes from x-ray powder diffraction scans showing peaks near the expected Bragg angles for InAs (004) and (002) reflections. A fourth indication comes from low-temperature photoluminescence measurements, which show a band at 0.5 eV associated with the dots 16. Since interdiffusion of Ga and In is possible during dot formation, the composition is not known in advance but can be determined as well. However, because of the small size of the dots, it is not possible at present to obtain electron microprobe data that directly corroborate the composition inferred from the photoluminescence measurement. On the other hand, analysis of the HR-TEM images of capped InAs dots permits a precise determination of the two lattice parameters present in a small region comprising all three types of material, i.e., dot 16, cap 20 and substrate 10.

An analysis may be performed by simulating the two-dimensional Fourier transform of the (110) zone axis image obtained in HR-TEM. The coordinates of the first eight reciprocal lattice vectors for both lattices are obtained from the spectrum of the TEM image using a center-of-intensity calculation. In the image of 1024 pixels square, the two sets of spots originating from the two lattice parameters are easily resolved. An averaging radius of five pixels is selected for locating the center of intensity of the individual peaks by iteration. Then a least-squares fitting procedure is applied to find the best estimate of the lattice parameter and rotation angle for each lattice in the image, by minimizing the root-mean-square error in the differences between the coordinates of the eight vectors representing the observed peaks and a corresponding set of coordinates of eight vectors representing the ideal (simulated) peaks. This process indicates that one lattice parameter is 6.6% larger than the other, and the two lattices have a relative tilt angle of 0.8 degrees. Direct visualization of the dot region and an estimate of the strain distribution may be obtained by the method of phase imaging (see, for example, MJ. Hytch, E. Snoeck, R. Kilaas, Ultramicroscopy 74, 131 (1998), and G. Ade and R. Lauer, Ultramicroscopy 77, 177 (1999)). Using the inferred reciprocal lattice vectors from the analysis just described, displacement fields can be calculated using either lattice as the reference. As shown in Fig. 9K, a set of interference fringes appears in the GaAs regions when the dot region is used as the reference of zero displacement, and vice versa when the substrate/cap region is used as reference, hi both cases, the observed strain field is approximately zero throughout the image region. Thus, the most likely conclusion is that the dot 16 material is fully relaxed, with an average composition corresponding to 6.6% misfit, that is, In_xGa₁-^As with x = 0.91. This estimate is in very close agreement with photoluminescence measurements.

It should again be noted, however, that in some embodiments of this invention it maybe desirable to produce quantum dots 16 that are in other than the substantially fully relaxed state.

hi general, it should be appreciated that the array 18 of quantum dots 16 in accordance with the embodiments of this invention maybe used in any device and for any application where quantum dots fabricated by conventional processes and methods are used_> or are considered for use.

It should also be appreciated that some of the features of the present invention could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the present invention, and not in limitation thereof.

Claims

CLAIMSWhat is claimed, is:

1. A method to fabricate an array of quantum dots, comprising:

forming an array of holes in a surface of a substrate through apertures in a mask;

removing the mask; and

epitaxially depositing a first semiconductor material into individual ones of the holes to form individual ones of the quantum dots.

2. A method as in claim 1, where the substrate is comprised of a first Group III- V compound, and where the semiconductor material is comprised of a second Group III- V compound.

3. A method as in claim 1, where the substrate is comprised of GaAs, and where the semiconductor material is comprised of InAs.

4. A method as in claim 1 , where removing the mask is followed by depositing a buffer layer of a second semiconductor material at least within individual ones of the holes.

5. A method as in claim 4, where the substrate is comprised of GaAs, where the semiconductor material is comprised of hiAs, and where the second semiconductor material is comprised of GaAs.

6. A method as in claim 1, where the mask is comprised of an anodic aluminum oxide (AAO) membrane.

7. A method as in claim 1, where forming the array of holes comprises use of a reactive ion etching process.

8. A method as in claim 1, where epitaxially depositing comprises a molecular beam epitaxy (MBE) process.

9. A method as in claim 1 , where the array of holes has a periodicity of about 100 nm and where each hole has a diameter of less than about 70 nm.

10. A method as in claim 1, comprising an initial step of passivating the surface of the substrate.

11. A method as in claim 1, further comprising forming a capping layer over individual ones of the quantum dots.

12. A method as in claim 11, where the semiconductor material is comprised of a first semiconductor material, and where the capping layer is comprised of a second semiconductor material.

13. A method as in claim 11 , where the semiconductor material is comprised of InAs, and where the capping layer is comprised of other than InAs.

14. A method as in claim 1, where the first semiconductor material of individual ones of the quantum dots is one of substantially relaxed, substantially strained or partially relaxed.

15. A method to fabricate an array of quantum dots, comprising:

providing a substrate comprised of GaAs;

reactive ion etching an array of holes into a surface of the GaAs substrate through apertures in a mask comprised of an anodic aluminum oxide (AAO) membrane;

removing the mask; depositing by molecular beam epitaxy a buffer layer comprised of GaAs at least within individual ones of the holes; and

depositing InAs by molecular beams epitaxy over the buffer layer in individual ones of the holes to form the array of quantum dots.

16. A array of quantum dots fabricated by a method comprising:

providing a substrate comprised of GaAs;

removing the mask;

depositing by molecular beam epitaxy a buffer layer comprised of GaAs at least within individual ones of the holes; and

depositing InAs by molecular beam epitaxy over the buffer layer in individual ones of the holes to form the array of quantum dots.

17. An array of quantum dots, each of said quantum dots comprising a substantially crystalline body comprised of a first semiconductor material that is substantially contained within a hole etched into a surface of a substrate.

18. An array of quantum dots as in claim 17, where the first semiconductor material is comprised of a first Group III-V material, and where the substrate is comprised of a second semiconductor material comprised of a second Group III-V material.

19. An array of quantum dots as in claim 17, where the first semiconductor material is comprised of InAs, and where the substrate is comprised of a second semiconductor material comprised of GaAs.

20. An array of quantum dots as in claim 17, further comprising a buffer layer interposed between the first semiconductor material and exposed substrate material within the hole that contains the first semiconductor material.

21. An array of quantum dots as in claim 17, where the first semiconductor material is comprised of InAs, where the second semiconductor material is comprised of GaAs, and where the buffer layer is comprised of GaAs.

22. An array of quantum dots as in claim 17, where the holes form an array of holes having a periodicity of about 100 run, where each hole has a diameter of less than about 70 nm.

23. An array of quantum dots as in claim 17, further comprising a capping layer disposed over an exposed portion of individual ones of the substantially crystalline bodies.

24. A method as in claim 17, where the substantially crystalline body of individual ones of the quantum dots is one of substantially relaxed, substantially strained or partially relaxed.

25. A device comprising an array of quantum dots, each of said quantum dots comprising a substantially crystalline body comprised of a semiconductor material that is substantially contained within a hole etched into a surface of a substrate.

26. A device as in claim 25, embodied as an emitter of electromagnetic radiation.

27. A device as in claim 25, embodied as a detector of electromagnetic radiation.

28. A device as in claim 25, embodied as an amplifier of electromagnetic radiation.

29. A device as in claim 25, embodied as a logic element.

30. A method to fabricate an array of quantum dots, comprising:

epitaxially depositing a first semiconductor material into individual ones of the holes to form individual ones of the quantum dots; and

removing the mask.

31. A method to fabricate an array of quantum dots, comprising:

epitaxially depositing a first semiconductor material into individual ones of the holes to form a buffer layer that lines individual ones of the holes;

epitaxially depositing a second semiconductor material into individual ones of the holes to form individual ones of the quantum dots; and

removing the mask.

32. A method as in claim 31, further comprising, before removing the mask, epitaxially depositing additional semiconductor material onto exposed portions of the second semiconductor material to form individual ones of capping layers.

33. A method of quantum dot synthesis comprising directing and confining growth of quantum dot material using a nano-cavity array that is imprinted into a substrate surface via a highly ordered nano-pore array template, where the template is formed and self-organized in an AAO membrane.