JP5400259B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5400259B2 JP5400259B2 JP2005172077A JP2005172077A JP5400259B2 JP 5400259 B2 JP5400259 B2 JP 5400259B2 JP 2005172077 A JP2005172077 A JP 2005172077A JP 2005172077 A JP2005172077 A JP 2005172077A JP 5400259 B2 JP5400259 B2 JP 5400259B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- line
- plate
- memory device
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4013—Memory devices with multiple cells per bit, e.g. twin-cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005172077A JP5400259B2 (ja) | 2004-11-19 | 2005-06-13 | 半導体記憶装置 |
| KR1020050109606A KR20060056249A (ko) | 2004-11-19 | 2005-11-16 | 반도체 기억장치 |
| US11/280,170 US7193884B2 (en) | 2004-11-19 | 2005-11-17 | Semiconductor memory device |
| US11/705,420 US20070139995A1 (en) | 2004-11-19 | 2007-02-13 | Semiconductor memory device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004335886 | 2004-11-19 | ||
| JP2004335886 | 2004-11-19 | ||
| JP2005172077A JP5400259B2 (ja) | 2004-11-19 | 2005-06-13 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006172683A JP2006172683A (ja) | 2006-06-29 |
| JP2006172683A5 JP2006172683A5 (enExample) | 2008-04-24 |
| JP5400259B2 true JP5400259B2 (ja) | 2014-01-29 |
Family
ID=36673238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005172077A Expired - Fee Related JP5400259B2 (ja) | 2004-11-19 | 2005-06-13 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7193884B2 (enExample) |
| JP (1) | JP5400259B2 (enExample) |
| KR (1) | KR20060056249A (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100673901B1 (ko) * | 2005-01-28 | 2007-01-25 | 주식회사 하이닉스반도체 | 저전압용 반도체 메모리 장치 |
| US7767992B2 (en) * | 2005-08-09 | 2010-08-03 | Ovonyx, Inc. | Multi-layer chalcogenide devices |
| US7375999B2 (en) * | 2005-09-29 | 2008-05-20 | Infineon Technologies Ag | Low equalized sense-amp for twin cell DRAMs |
| KR100823706B1 (ko) * | 2006-07-21 | 2008-04-21 | 삼성전자주식회사 | 반도체 장치의 신호 라인 구조물 및 이를 제조하는 방법 |
| DE102006035076B4 (de) * | 2006-07-28 | 2010-04-08 | Qimonda Ag | Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines integrierten Halbleiterspeichers |
| KR100846392B1 (ko) * | 2006-08-31 | 2008-07-15 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| DE102007012902B3 (de) * | 2007-03-19 | 2008-07-10 | Qimonda Ag | Kopplungsoptimierte Anschlusskonfiguration von Signalleitungen und Verstärkern |
| JP2008243238A (ja) * | 2007-03-23 | 2008-10-09 | Elpida Memory Inc | 分子電池メモリ装置 |
| DE102007023653A1 (de) * | 2007-05-22 | 2008-11-27 | Qimonda Ag | Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers |
| US7759714B2 (en) * | 2007-06-26 | 2010-07-20 | Hitachi, Ltd. | Semiconductor device |
| US7933141B2 (en) | 2008-04-04 | 2011-04-26 | Elpida Memory, Inc. | Semiconductor memory device |
| TW201142869A (en) * | 2010-02-09 | 2011-12-01 | Samsung Electronics Co Ltd | Memory device from which dummy edge memory block is removed |
| KR101223539B1 (ko) * | 2010-12-15 | 2013-01-21 | 에스케이하이닉스 주식회사 | 반도체 집적 회로 장치 |
| US8743591B2 (en) * | 2011-04-26 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device and method for driving the same |
| KR20120126437A (ko) * | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
| KR20130057855A (ko) * | 2011-11-24 | 2013-06-03 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
| JP2014149884A (ja) | 2013-01-31 | 2014-08-21 | Micron Technology Inc | 半導体装置 |
| US20140219007A1 (en) * | 2013-02-07 | 2014-08-07 | Nvidia Corporation | Dram with segmented page configuration |
| JP2014225566A (ja) * | 2013-05-16 | 2014-12-04 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
| JP6359332B2 (ja) * | 2014-05-09 | 2018-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US20200105336A1 (en) * | 2018-09-28 | 2020-04-02 | Omnivision Technologies, Inc. | Fast access dram with 2 cell-per-bit, common word line, architecture |
| US12051464B2 (en) * | 2021-04-29 | 2024-07-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor memory devices with different word lines |
| US20250287608A1 (en) * | 2024-03-08 | 2025-09-11 | International Business Machines Corporation | Pillar critical dimension reduction by isotropic plasma etching with high selectivity to silicon-containing antireflective coating and silicon nitride |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2765856B2 (ja) * | 1988-06-17 | 1998-06-18 | 株式会社日立製作所 | メモリ回路 |
| JPH0334188A (ja) * | 1989-06-30 | 1991-02-14 | Hitachi Ltd | メモリ回路 |
| TW235363B (enExample) * | 1993-01-25 | 1994-12-01 | Hitachi Seisakusyo Kk | |
| JPH08115595A (ja) * | 1994-10-14 | 1996-05-07 | Matsushita Electric Ind Co Ltd | メモリ装置 |
| US5825609A (en) * | 1996-04-23 | 1998-10-20 | International Business Machines Corporation | Compound electrode stack capacitor |
| KR100224702B1 (ko) * | 1997-06-17 | 1999-10-15 | 윤종용 | 기준 셀 커패시터로 선형 커패시터를 사용하는 강유전체 메모리소자, 그에 저장된 정보를 읽는 방법 및 그 제조방법 |
| JPH11260054A (ja) * | 1998-01-08 | 1999-09-24 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
| JP3617615B2 (ja) * | 1999-11-08 | 2005-02-09 | シャープ株式会社 | 強誘電体記憶装置 |
| JP2001308288A (ja) * | 2000-04-27 | 2001-11-02 | Sharp Corp | 半導体装置の製造方法および半導体装置 |
| JP3856424B2 (ja) * | 2000-12-25 | 2006-12-13 | 株式会社東芝 | 半導体記憶装置 |
| US6545923B2 (en) * | 2001-05-04 | 2003-04-08 | Samsung Electronics Co., Ltd. | Negatively biased word line scheme for a semiconductor memory device |
| JP2003092364A (ja) * | 2001-05-21 | 2003-03-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2004213722A (ja) * | 2002-12-27 | 2004-07-29 | Matsushita Electric Ind Co Ltd | 半導体記憶装置及び半導体集積回路装置 |
-
2005
- 2005-06-13 JP JP2005172077A patent/JP5400259B2/ja not_active Expired - Fee Related
- 2005-11-16 KR KR1020050109606A patent/KR20060056249A/ko not_active Ceased
- 2005-11-17 US US11/280,170 patent/US7193884B2/en not_active Expired - Fee Related
-
2007
- 2007-02-13 US US11/705,420 patent/US20070139995A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20060158924A1 (en) | 2006-07-20 |
| US20070139995A1 (en) | 2007-06-21 |
| KR20060056249A (ko) | 2006-05-24 |
| JP2006172683A (ja) | 2006-06-29 |
| US7193884B2 (en) | 2007-03-20 |
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