JP5367523B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP5367523B2
JP5367523B2 JP2009221078A JP2009221078A JP5367523B2 JP 5367523 B2 JP5367523 B2 JP 5367523B2 JP 2009221078 A JP2009221078 A JP 2009221078A JP 2009221078 A JP2009221078 A JP 2009221078A JP 5367523 B2 JP5367523 B2 JP 5367523B2
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Prior art keywords
layer
wiring
wiring board
organic substrate
laminate
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JP2009221078A
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English (en)
Japanese (ja)
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JP2011071315A (ja
JP2011071315A5 (https=
Inventor
昌宏 春原
啓介 上田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009221078A priority Critical patent/JP5367523B2/ja
Priority to US12/884,271 priority patent/US8212365B2/en
Publication of JP2011071315A publication Critical patent/JP2011071315A/ja
Publication of JP2011071315A5 publication Critical patent/JP2011071315A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2009221078A 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法 Active JP5367523B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009221078A JP5367523B2 (ja) 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法
US12/884,271 US8212365B2 (en) 2009-09-25 2010-09-17 Printed wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009221078A JP5367523B2 (ja) 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2011071315A JP2011071315A (ja) 2011-04-07
JP2011071315A5 JP2011071315A5 (https=) 2012-08-23
JP5367523B2 true JP5367523B2 (ja) 2013-12-11

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Family Applications (1)

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JP2009221078A Active JP5367523B2 (ja) 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US8212365B2 (https=)
JP (1) JP5367523B2 (https=)

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JP5833398B2 (ja) * 2011-06-27 2015-12-16 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
JP5561254B2 (ja) * 2011-07-29 2014-07-30 株式会社村田製作所 回路モジュール及び複合回路モジュール
US8780576B2 (en) 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US8836478B2 (en) * 2011-09-25 2014-09-16 Authentec, Inc. Electronic device including finger sensor and related methods
JP5778557B2 (ja) * 2011-11-28 2015-09-16 新光電気工業株式会社 半導体装置の製造方法、半導体装置、及び半導体素子
JP2013123907A (ja) * 2011-12-16 2013-06-24 Panasonic Corp 金属張積層板、及びプリント配線板
DE112011105967T5 (de) * 2011-12-20 2014-09-25 Intel Corporation Mikroelektronisches Gehäuse und gestapelte mikroelektronische Baugruppe und Rechensystem mit denselben
JP2013243263A (ja) * 2012-05-21 2013-12-05 Internatl Business Mach Corp <Ibm> ３次元積層パッケージにおける電力供給と放熱（冷却）との両立
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KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
US10672695B2 (en) * 2015-12-23 2020-06-02 Intel Corporation Multi-layer molded substrate with graded CTE
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JP2011071315A (ja) 2011-04-07
US20110074046A1 (en) 2011-03-31
US8212365B2 (en) 2012-07-03

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