JP5320689B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5320689B2 JP5320689B2 JP2007126017A JP2007126017A JP5320689B2 JP 5320689 B2 JP5320689 B2 JP 5320689B2 JP 2007126017 A JP2007126017 A JP 2007126017A JP 2007126017 A JP2007126017 A JP 2007126017A JP 5320689 B2 JP5320689 B2 JP 5320689B2
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- JP
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- Prior art keywords
- insulating film
- effect transistor
- field effect
- forming
- gate electrode
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
以下、本発明の実施の形態1に係る半導体装置の製造方法について図面を参照しながら説明する。
以下、本発明の実施の形態2に係る半導体装置の製造方法について図面を参照しながら説明する。
以下、本発明の実施の形態3に係る半導体装置の製造方法について図面を参照しながら説明する。
以下、本発明の実施の形態4に係る半導体装置の製造方法について図面を参照しながら説明する。
12 T型ゲート電極
15 電界効果トランジスタ
16 SiO2膜(保護絶縁膜)
17 下部電極
18 フッ素系ポリマー層(犠牲層)
20 SiN膜(容量絶縁膜)
23 上部電極
24 ポリイミド(ポジ型の感光性材料)
25 ポリイミド(ネガ型の感光性材料)
Claims (2)
- 半導体基板上に、T型ゲート電極を有する電界効果トランジスタを形成し、前記電界効果トランジスタの前記T型ゲート電極を保護絶縁膜で覆う工程と、
前記半導体基板上にMIMキャパシタの下部電極を形成する工程と、
前記電界効果トランジスタの能動部分を犠牲層で覆う工程と、
前記犠牲層及び前記下部電極上にMIMキャパシタの容量絶縁膜を形成する工程と、
前記犠牲層上の前記容量絶縁膜を除去した後に、前記保護絶縁膜及び前記容量絶縁膜に対して選択的に前記犠牲層を除去する工程と、
前記容量絶縁膜を介して前記下部電極上にMIMキャパシタの上部電極を形成する工程とを備え、
前記保護絶縁膜としてSiO 2 膜を用い、
前記容量絶縁膜としてSiN膜を用い、
前記犠牲層としてフッ素系ポリマーを用い、
前記犠牲層を除去する工程において、O 2 プラズマに晒すことにより前記保護絶縁膜及び前記容量絶縁膜に対して選択的に前記犠牲層を除去することを特徴とする半導体装置の製造方法。 - 半導体基板上に、T型ゲート電極を有する電界効果トランジスタを形成する工程と、
前記半導体基板上にMIMキャパシタの下部電極を形成する工程と、
前記電界効果トランジスタ上にネガ型の感光性材料を塗布し、前記T型ゲート電極の傘下部分が未露光となるように前記電界効果トランジスタの能動部分を露光し、現像して前記電界効果トランジスタ周囲に前記感光性材料を残留させつつ前記T型ゲート電極の傘下部分に中空部を形成する工程と、
少なくとも前記下部電極上にMIMキャパシタの容量絶縁膜を形成する工程と、
前記容量絶縁膜を介して前記下部電極上にMIMキャパシタの上部電極を形成する工程とを備えることを特徴とする半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007126017A JP5320689B2 (ja) | 2007-05-10 | 2007-05-10 | 半導体装置の製造方法 |
US11/969,990 US7625789B2 (en) | 2007-05-10 | 2008-01-07 | Method for manufacturing semiconductor device |
DE102008010328A DE102008010328A1 (de) | 2007-05-10 | 2008-02-21 | Verfahren zum Herstellen einer Halbleitervorrichtung |
FR0851445A FR2916083B1 (fr) | 2007-05-10 | 2008-03-05 | Procede de fabrication d'un dispositif a semiconducteur comportant un transistor fet avec grille en t |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007126017A JP5320689B2 (ja) | 2007-05-10 | 2007-05-10 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008282997A JP2008282997A (ja) | 2008-11-20 |
JP5320689B2 true JP5320689B2 (ja) | 2013-10-23 |
Family
ID=39868958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007126017A Expired - Fee Related JP5320689B2 (ja) | 2007-05-10 | 2007-05-10 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7625789B2 (ja) |
JP (1) | JP5320689B2 (ja) |
DE (1) | DE102008010328A1 (ja) |
FR (1) | FR2916083B1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010067692A (ja) * | 2008-09-09 | 2010-03-25 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US20110053336A1 (en) * | 2009-09-03 | 2011-03-03 | Raytheon Company | Method for selective deposition of dielectric layers on semiconductor structures |
US9293379B2 (en) * | 2009-09-03 | 2016-03-22 | Raytheon Company | Semiconductor structure with layers having different hydrogen contents |
US9082722B2 (en) * | 2013-03-25 | 2015-07-14 | Raytheon Company | Monolithic integrated circuit (MMIC) structure and method for forming such structure |
US9490282B2 (en) | 2015-03-19 | 2016-11-08 | Omnivision Technologies, Inc. | Photosensitive capacitor pixel for image sensor |
US9478652B1 (en) | 2015-04-10 | 2016-10-25 | Raytheon Company | Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04328867A (ja) * | 1991-04-30 | 1992-11-17 | Sekiyu Sangyo Kasseika Center | 赤外線検出器 |
JPH05129345A (ja) * | 1991-11-08 | 1993-05-25 | Toshiba Corp | マイクロ波集積回路の製造方法 |
JP2522159B2 (ja) | 1993-06-24 | 1996-08-07 | 日本電気株式会社 | 半導体集積回路の製造方法 |
JP2605647B2 (ja) | 1993-12-27 | 1997-04-30 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3226808B2 (ja) * | 1996-11-26 | 2001-11-05 | ルーセント テクノロジーズ インコーポレイテッド | 集積回路チップを製造する方法 |
JP2000138237A (ja) * | 1998-11-02 | 2000-05-16 | Nec Corp | 感光性有機膜を有する半導体装置及びその製造方法 |
KR100827437B1 (ko) * | 2006-05-22 | 2008-05-06 | 삼성전자주식회사 | Mim 커패시터를 구비하는 반도체 집적 회로 장치 및이의 제조 방법 |
-
2007
- 2007-05-10 JP JP2007126017A patent/JP5320689B2/ja not_active Expired - Fee Related
-
2008
- 2008-01-07 US US11/969,990 patent/US7625789B2/en not_active Expired - Fee Related
- 2008-02-21 DE DE102008010328A patent/DE102008010328A1/de not_active Withdrawn
- 2008-03-05 FR FR0851445A patent/FR2916083B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20080280400A1 (en) | 2008-11-13 |
JP2008282997A (ja) | 2008-11-20 |
FR2916083B1 (fr) | 2011-11-25 |
FR2916083A1 (fr) | 2008-11-14 |
US7625789B2 (en) | 2009-12-01 |
DE102008010328A1 (de) | 2008-11-20 |
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