JP5295603B2 - Esd保護素子及びその製造方法 - Google Patents
Esd保護素子及びその製造方法 Download PDFInfo
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- JP5295603B2 JP5295603B2 JP2008082342A JP2008082342A JP5295603B2 JP 5295603 B2 JP5295603 B2 JP 5295603B2 JP 2008082342 A JP2008082342 A JP 2008082342A JP 2008082342 A JP2008082342 A JP 2008082342A JP 5295603 B2 JP5295603 B2 JP 5295603B2
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- JP
- Japan
- Prior art keywords
- region
- esd protection
- drain region
- protection element
- mos structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000012535 impurity Substances 0.000 claims description 56
- 230000015572 biosynthetic process Effects 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 25
- 230000015556 catabolic process Effects 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- 238000010521 absorption reaction Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 32
- 239000010410 layer Substances 0.000 description 17
- 108091006146 Channels Proteins 0.000 description 10
- 230000004913 activation Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000002346 layers by function Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
11 半導体基板
12 ドレイン領域
13 ソース領域
14 ゲート電極
15 ソース電極
17 ゲート電極
20 MOS構造
22 不純物活性領域
23 素子分離領域
25 Pウエル
26 ウエル電極
Claims (7)
- 半導体機能素子層内に形成されたMOS構造を含み、前記MOS構造のドレイン領域をサージ吸収端とするESD保護素子であって、
前記MOS構造を囲む素子分離領域と、
前記MOS構造のドレイン領域に接して前記ドレイン領域と前記素子分離領域との間に形成され、前記ドレイン領域とPN接合を形成する接合形成領域と、を含み、
前記ドレイン領域は、前記接合形成領域と接触する部分に、前記ドレイン領域よりも低濃度のドープドレイン領域を更に含むことを特徴とするESD保護素子。 - 前記接合形成領域は、前記ドレイン領域の少なくとも一部を囲むことを特徴とする請求項1に記載のESD保護素子。
- 前記接合形成領域の不純物濃度は、前記MOS構造のチャネル領域の不純物濃度より高いことを特徴とする請求項1又は2に記載のESD保護素子。
- 前記接合形成領域のブレークダウン電圧が、前記MOS構造のブレークダウン電圧より低いことを特徴とする請求項1乃至3のいずれか1に記載のESD保護素子。
- 半導体基板上に素子分離領域によって囲まれたMOS構造を含む半導体機能素子層を形成する素子形成工程と、
前記MOSトランジスタのドレイン領域と前記素子分離領域との間に、前記ドレイン領域に接して前記ドレイン領域とPN接合を形成する接合形成領域を形成する調整層形成工程と、
当該調整層形成後の半導体機能素子層上に絶縁層を形成する絶縁層形成工程と、を有し、
前記ドレイン領域は、前記接合形成領域と接触する部分に、前記ドレイン領域よりも低濃度のドープドレイン領域を更に含むことを特徴とするESD保護素子の製造方法。 - 前記調整層形成工程においては、前記ドレイン領域の少なくとも一部を囲むように前記接合形成領域を形成することを特徴とする請求項5に記載のESD保護素子の製造方法。
- 前記調整層形成工程においては、前記接合形成領域の不純物濃度を前記MOS構造のチャネル領域の不純物濃度より高く調整することを特徴とする請求項5又は6に記載のESD保護素子の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008082342A JP5295603B2 (ja) | 2008-03-27 | 2008-03-27 | Esd保護素子及びその製造方法 |
US12/379,933 US8159033B2 (en) | 2008-03-27 | 2009-03-04 | ESD protection device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008082342A JP5295603B2 (ja) | 2008-03-27 | 2008-03-27 | Esd保護素子及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009238973A JP2009238973A (ja) | 2009-10-15 |
JP5295603B2 true JP5295603B2 (ja) | 2013-09-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008082342A Active JP5295603B2 (ja) | 2008-03-27 | 2008-03-27 | Esd保護素子及びその製造方法 |
Country Status (2)
Country | Link |
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US (1) | US8159033B2 (ja) |
JP (1) | JP5295603B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102082144B (zh) * | 2010-11-04 | 2013-03-20 | 中国科学院上海微系统与信息技术研究所 | 一种soi电路中的esd保护结构及制作方法 |
JP5990986B2 (ja) | 2012-04-10 | 2016-09-14 | 三菱電機株式会社 | 保護ダイオード |
US10483258B2 (en) * | 2017-02-25 | 2019-11-19 | Indian Institute Of Science | Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
JP3016251B2 (ja) * | 1989-08-15 | 2000-03-06 | 富士通株式会社 | 半導体装置 |
JPH05235283A (ja) | 1992-02-25 | 1993-09-10 | Matsushita Electron Corp | Mos型入力保護回路装置 |
JPH11233641A (ja) * | 1998-02-10 | 1999-08-27 | Seiko Epson Corp | 半導体装置及び半導体装置の製造方法 |
JP4076261B2 (ja) * | 1998-03-06 | 2008-04-16 | セイコーNpc株式会社 | 半導体装置 |
JP3422313B2 (ja) | 2000-06-08 | 2003-06-30 | セイコーエプソン株式会社 | 静電気保護回路が内蔵された半導体装置 |
TW502459B (en) * | 2001-01-03 | 2002-09-11 | Taiwan Semiconductor Mfg | Diode structure with high electrostatic discharge protection and electrostatic discharge protection circuit design of the diode |
JP4127007B2 (ja) * | 2002-09-30 | 2008-07-30 | ミツミ電機株式会社 | 半導体装置 |
US7217984B2 (en) * | 2005-06-17 | 2007-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Divided drain implant for improved CMOS ESD performance |
-
2008
- 2008-03-27 JP JP2008082342A patent/JP5295603B2/ja active Active
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2009
- 2009-03-04 US US12/379,933 patent/US8159033B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2009238973A (ja) | 2009-10-15 |
US8159033B2 (en) | 2012-04-17 |
US20090242993A1 (en) | 2009-10-01 |
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