JP5206878B2 - 樹脂多層基板及び該樹脂多層基板の製造方法 - Google Patents
樹脂多層基板及び該樹脂多層基板の製造方法 Download PDFInfo
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- 229920005989 resin Polymers 0.000 title claims description 343
- 239000011347 resin Substances 0.000 title claims description 343
- 239000000758 substrate Substances 0.000 title claims description 106
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 239000004020 conductor Substances 0.000 claims description 134
- 238000000034 method Methods 0.000 claims description 19
- 230000006854 communication Effects 0.000 claims description 9
- 238000003825 pressing Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 22
- 239000002184 metal Substances 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000011888 foil Substances 0.000 description 18
- 238000009413 insulation Methods 0.000 description 6
- 238000005553 drilling Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
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Description
図1は、本発明の実施の形態1に係る樹脂多層基板の構成を示す模式図である。図1に示すように、実施の形態1に係る樹脂多層基板1は、ベース層10、部品内蔵層(第1樹脂層)20、薄層樹脂層(第2樹脂層)30を順に積層してある。ベース層10は、セラミック、ガラス、エポキシ樹脂等で構成され、両面に配線パターン11a、11bが形成してある。ベース層10の、配線パターン11aが形成してある面には、IC素子12が、配線パターン11bが形成してある面には複数の電子部品13がはんだ等の導電性接合材(図示せず)を用いて実装されている。複数の電子部品13は、表面実装型の部品であり、例えばチップコンデンサ、抵抗等である。配線パターン11aは、ベース層10に形成してある複数のビア導体14を介して配線パターン11bと電気的に接続している。また、配線パターン11a、11bの所定位置には、絶縁性を確保する等の理由からレジスト層15が形成してある。
図14及び図15は、本発明の実施の形態2に係る樹脂多層基板1の製造方法を説明するための模式図である。図14は、連接したビアホール21、31に導電性ペースト22を充填した後の薄層樹脂層30に金属箔40を貼り付け、薄層樹脂層30の方向に金属箔40を加圧する状態を、図15は、薄層樹脂層30の方向に金属箔40を加圧した後の状態を、それぞれ示している。本実施の形態2に係る樹脂多層基板1の製造方法は、保持フィルム38を薄層樹脂層30に貼り付けず、薄層樹脂層30単体を部品内蔵層20に積層する以外、図2から図8で示した実施の形態1の製造方法と同じであるため、詳細な説明を省略する。なお、図14及び図15では、樹脂多層基板1に形成した連接するビア導体23、33とその近傍部分について図示しているが、他の構成については図1に示す樹脂多層基板1の構成と同じであるため図示を省略している。
図16は、本発明の実施の形態3に係る樹脂多層基板1のビアホール21、31の構成を示す模式図である。なお、図16では、樹脂多層基板1に形成した連接するビア導体23、33とその近傍部分について図示しているが、他の構成については図1に示す樹脂多層基板1の構成と同じであるため図示を省略している。なお、図16では、説明のためにビアホール21のテーパー角が段階的に変化する例を示しているが、実際の樹脂多層基板1では、ビアホール21のテーパー角は連続的に変化している。なお、テーパー角とは、配線パターン11bが形成されたベース層10の面に対する垂線と、ビアホール21が形成された部品内蔵層20の面とのなす角度をいう。
10 ベース層
20 部品内蔵層
30 薄層樹脂層
11a、11b 配線パターン
12 IC素子
13 電子部品
14、23、33 ビア導体
15、36 レジスト層
21、31 ビアホール
22 導電性ペースト
34 表面電極
35 ビア導体の内部へ突き出した形状
38 保持フィルム
Claims (12)
- 第1樹脂層と、該第1樹脂層の一面に積層してある第2樹脂層とを備える樹脂多層基板において、
前記第2樹脂層の、前記第1樹脂層に積層されている面とは反対側の面に形成してある表面電極と、
前記第1樹脂層に設けてあり、一端が前記第1樹脂層の前記一面に至る第1ビア導体と、
前記第2樹脂層に設けてあり、一端が前記表面電極と、他端が前記第1ビア導体とそれぞれ電気的に接続してある第2ビア導体と
を備え、
前記第2ビア導体と接する前記第2樹脂層の少なくとも一部が、前記第1ビア導体の内部へ突き出した形状を形成していることを特徴とする樹脂多層基板。 - 少なくとも一面に配線パターンを形成してあるベース層を備え、
前記配線パターンが形成してある前記ベース層の一面に、前記第1樹脂層、前記第2樹脂層を順に積層し、前記配線パターンと前記第1ビア導体とを電気的に接続してあることを特徴とする請求項1に記載の樹脂多層基板。 - 前記第1樹脂層の、前記第2樹脂層が積層してある面とは反対側の面に形成してある配線パターンと、
前記第1樹脂層に内蔵し、前記配線パターンに実装してある電子部品とを備えることを特徴とする請求項1に記載の樹脂多層基板。 - 前記ベース層の少なくとも一面に電子部品を実装し、実装してある前記電子部品を前記第1樹脂層に内蔵してあることを特徴とする請求項2に記載の樹脂多層基板。
- 前記表面電極は、マザー基板に形成されている電極と電気的に接続してあることを特徴とする請求項1乃至4のいずれか一項に記載の樹脂多層基板。
- 前記第1ビア導体は、前記第2樹脂層の近傍部分のテーパー角が他の部分のテーパー角よりも大きくなるように形成してあることを特徴とする請求項1乃至5のいずれか一項に記載の樹脂多層基板。
- 第1樹脂層と、該第1樹脂層の一面に積層してある第2樹脂層とを備える樹脂多層基板を製造する方法において、
硬化状態の第1樹脂層に第1ビアホールを形成する第1工程と、
未硬化状態の第2樹脂層に第2ビアホールを形成し、前記第1ビアホールと前記第2ビアホールとが連接するように、前記第1樹脂層の一面に前記第2樹脂層を積層する第2工程と、
前記第1ビアホール及び前記第2ビアホールに導電性ペーストを充填して第1ビア導体及び第2ビア導体を形成する第3工程と、
前記第2ビア導体と接する前記第2樹脂層の少なくとも一部を、前記第1ビア導体の内部へ突き出す第4工程と、
前記導電性ペースト及び前記第2樹脂層を硬化状態にする第5工程と
を含むことを特徴とする樹脂多層基板の製造方法。 - 前記第3工程では、
前記第1ビアホール及び前記第2ビアホールに導電性ペーストを充填した場合、前記第2ビアホールから少なくとも上に凸形状を有するように前記導電性ペーストがはみ出し、
前記第4工程では、
前記第2ビアホールからはみ出した前記導電性ペーストを、前記導電性ペーストがはみ出した側の前記第2ビアホールの断面積よりも大きい断面積を有する物体で、前記第2ビアホール内へ押し込むことで、前記第2ビア導体と接する前記第2樹脂層の少なくとも一部を、前記第1ビア導体の内部へ突き出すことを特徴とする請求項7に記載の樹脂多層基板の製造方法。 - 未硬化状態の前記第2樹脂層の一面に、前記第2樹脂層の形状を保持する保持フィルムが貼り付けられ、貼り付けられた保持フィルムに前記第2樹脂層に形成した前記第2ビアホールと連接する第3ビアホールが形成してあり、
前記第3工程では、前記第1ビアホール、前記第2ビアホール、前記第3ビアホールに導電性ペーストを充填し、
前記第3工程の終了後に、前記保持フィルムを前記第2樹脂層から剥離することで、前記保持フィルムに形成してある前記第3ビアホールに充填されている前記導電性ペーストを、前記第2ビアホールからはみ出した前記導電性ペーストとすることを特徴とする請求項8に記載の樹脂多層基板の製造方法。 - 前記第4工程では、
前記第2樹脂層を前記第1樹脂層の方向に加圧することで、前記第2ビア導体と接する前記第2樹脂層の少なくとも一部を、前記第1ビア導体の内部へ突き出すことを特徴とする請求項7に記載の樹脂多層基板の製造方法。 - 前記第1工程では、
前記第2樹脂層の近傍部分のテーパー角が、他の部分のテーパー角よりも大きくなるように前記第1ビアホールを形成することを特徴とする請求項7に記載の樹脂多層基板の製造方法。 - 前記第2工程では、
前記第1樹脂層の一面に前記第2樹脂層を積層した後、前記第1ビアホール及び前記第2ビアホールに対して連通処理を行うことを特徴とする請求項7に記載の樹脂多層基板の製造方法。
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TWI565378B (zh) * | 2012-12-31 | 2017-01-01 | 三星電機股份有限公司 | 電路板及其製造方法 |
JP5999063B2 (ja) | 2013-10-08 | 2016-09-28 | 株式会社村田製作所 | セラミック多層基板 |
WO2015068555A1 (ja) * | 2013-11-07 | 2015-05-14 | 株式会社村田製作所 | 多層基板およびその製造方法 |
US9510454B2 (en) * | 2014-02-28 | 2016-11-29 | Qualcomm Incorporated | Integrated interposer with embedded active devices |
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JP2016004889A (ja) * | 2014-06-17 | 2016-01-12 | イビデン株式会社 | プリント配線板 |
US9281284B2 (en) * | 2014-06-20 | 2016-03-08 | Freescale Semiconductor Inc. | System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof |
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JP6863244B2 (ja) | 2017-11-20 | 2021-04-21 | 株式会社村田製作所 | 電子部品および電子部品の製造方法 |
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CN102484950B (zh) | 2014-12-31 |
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