JP5174355B2 - 配線基板及びその製造方法と半導体装置 - Google Patents

配線基板及びその製造方法と半導体装置 Download PDF

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Publication number
JP5174355B2
JP5174355B2 JP2007024228A JP2007024228A JP5174355B2 JP 5174355 B2 JP5174355 B2 JP 5174355B2 JP 2007024228 A JP2007024228 A JP 2007024228A JP 2007024228 A JP2007024228 A JP 2007024228A JP 5174355 B2 JP5174355 B2 JP 5174355B2
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Japan
Prior art keywords
wiring board
unit
substrate
unit wiring
wiring pattern
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JP2007024228A
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Japanese (ja)
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JP2008192740A (ja
JP2008192740A5 (https=
Inventor
直 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2007024228A priority Critical patent/JP5174355B2/ja
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Publication of JP2008192740A5 publication Critical patent/JP2008192740A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007024228A 2007-02-02 2007-02-02 配線基板及びその製造方法と半導体装置 Active JP5174355B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007024228A JP5174355B2 (ja) 2007-02-02 2007-02-02 配線基板及びその製造方法と半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007024228A JP5174355B2 (ja) 2007-02-02 2007-02-02 配線基板及びその製造方法と半導体装置

Publications (3)

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JP2008192740A JP2008192740A (ja) 2008-08-21
JP2008192740A5 JP2008192740A5 (https=) 2010-02-12
JP5174355B2 true JP5174355B2 (ja) 2013-04-03

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ID=39752576

Family Applications (1)

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JP2007024228A Active JP5174355B2 (ja) 2007-02-02 2007-02-02 配線基板及びその製造方法と半導体装置

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JP (1) JP5174355B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5577760B2 (ja) * 2009-03-09 2014-08-27 新光電気工業株式会社 パッケージ基板および半導体装置の製造方法
DE112018007290T5 (de) * 2018-03-16 2020-12-10 Mitsubishi Electric Corporation Substrat-Bondingstruktur und Substrat-Bondingverfahren
JP2023006236A (ja) * 2021-06-30 2023-01-18 株式会社オートネットワーク技術研究所 回路構成体及び電気接続箱

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0383396A (ja) * 1989-08-28 1991-04-09 Fujitsu Ltd 多層プリント配線板
JPH08181417A (ja) * 1994-12-26 1996-07-12 Furukawa Electric Co Ltd:The 回路材の製造方法
JP3553043B2 (ja) * 2001-01-19 2004-08-11 松下電器産業株式会社 部品内蔵モジュールとその製造方法
JP2004014679A (ja) * 2002-06-05 2004-01-15 Fcm Kk 積層用回路基板および積層回路

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JP2008192740A (ja) 2008-08-21

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