JP5147677B2 - 樹脂封止パッケージの製造方法 - Google Patents

樹脂封止パッケージの製造方法 Download PDF

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Publication number
JP5147677B2
JP5147677B2 JP2008328365A JP2008328365A JP5147677B2 JP 5147677 B2 JP5147677 B2 JP 5147677B2 JP 2008328365 A JP2008328365 A JP 2008328365A JP 2008328365 A JP2008328365 A JP 2008328365A JP 5147677 B2 JP5147677 B2 JP 5147677B2
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Japan
Prior art keywords
resin
support
adhesive layer
package
electronic component
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JP2008328365A
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English (en)
Japanese (ja)
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JP2010153498A (ja
JP2010153498A5 (enExample
Inventor
裕治 国本
昭彦 立岩
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008328365A priority Critical patent/JP5147677B2/ja
Priority to US12/644,407 priority patent/US8399977B2/en
Publication of JP2010153498A publication Critical patent/JP2010153498A/ja
Publication of JP2010153498A5 publication Critical patent/JP2010153498A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2008328365A 2008-12-24 2008-12-24 樹脂封止パッケージの製造方法 Active JP5147677B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008328365A JP5147677B2 (ja) 2008-12-24 2008-12-24 樹脂封止パッケージの製造方法
US12/644,407 US8399977B2 (en) 2008-12-24 2009-12-22 Resin-sealed package and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008328365A JP5147677B2 (ja) 2008-12-24 2008-12-24 樹脂封止パッケージの製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012179403A Division JP5456113B2 (ja) 2012-08-13 2012-08-13 樹脂封止パッケージ

Publications (3)

Publication Number Publication Date
JP2010153498A JP2010153498A (ja) 2010-07-08
JP2010153498A5 JP2010153498A5 (enExample) 2011-11-17
JP5147677B2 true JP5147677B2 (ja) 2013-02-20

Family

ID=42264825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008328365A Active JP5147677B2 (ja) 2008-12-24 2008-12-24 樹脂封止パッケージの製造方法

Country Status (2)

Country Link
US (1) US8399977B2 (enExample)
JP (1) JP5147677B2 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5734624B2 (ja) * 2010-11-12 2015-06-17 新光電気工業株式会社 半導体パッケージの製造方法
JP2013098433A (ja) * 2011-11-02 2013-05-20 Hitachi Ltd プリント基板の製造方法及びその製造方法によって製造されたプリント基板
US9425122B2 (en) * 2012-12-21 2016-08-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
JP5624696B1 (ja) 2012-12-21 2014-11-12 パナソニック株式会社 電子部品パッケージおよびその製造方法
US9595651B2 (en) 2012-12-21 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
JP5624699B1 (ja) 2012-12-21 2014-11-12 パナソニック株式会社 電子部品パッケージおよびその製造方法
US20150206819A1 (en) * 2012-12-21 2015-07-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
US9576930B2 (en) * 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
US20150206855A1 (en) * 2014-01-22 2015-07-23 Mediatek Inc. Semiconductor package
JP6354285B2 (ja) * 2014-04-22 2018-07-11 オムロン株式会社 電子部品を埋設した樹脂構造体およびその製造方法
US9786631B2 (en) * 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
JP6610498B2 (ja) * 2016-10-21 2019-11-27 株式会社村田製作所 複合型電子部品の製造方法
EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
KR102702093B1 (ko) * 2019-11-27 2024-09-04 삼성전자주식회사 반도체 패키지
US12315776B2 (en) * 2021-11-08 2025-05-27 Analog Devices, Inc. Integrated device package with an integrated heat sink
US20250240893A1 (en) * 2024-01-19 2025-07-24 Advanced Semiconductor Engineering, Inc. Package structure

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US6586836B1 (en) * 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
JP2001352021A (ja) * 2000-06-07 2001-12-21 Sony Corp 半導体パッケージ、半導体パッケージの実装構造及び半導体パッケージの製造方法
WO2002027786A1 (en) * 2000-09-25 2002-04-04 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
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Publication number Publication date
US8399977B2 (en) 2013-03-19
JP2010153498A (ja) 2010-07-08
US20100155925A1 (en) 2010-06-24

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