JP5144294B2 - リードフレームおよびそれを用いた回路装置の製造方法 - Google Patents

リードフレームおよびそれを用いた回路装置の製造方法 Download PDF

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Publication number
JP5144294B2
JP5144294B2 JP2008025930A JP2008025930A JP5144294B2 JP 5144294 B2 JP5144294 B2 JP 5144294B2 JP 2008025930 A JP2008025930 A JP 2008025930A JP 2008025930 A JP2008025930 A JP 2008025930A JP 5144294 B2 JP5144294 B2 JP 5144294B2
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Japan
Prior art keywords
lead frame
support portion
units
groove
island
Prior art date
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Active
Application number
JP2008025930A
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English (en)
Japanese (ja)
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JP2009188150A (ja
JP2009188150A5 (enExample
Inventor
哲也 福島
崇 北澤
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On Semiconductor Trading Ltd
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On Semiconductor Trading Ltd
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Filing date
Publication date
Application filed by On Semiconductor Trading Ltd filed Critical On Semiconductor Trading Ltd
Priority to JP2008025930A priority Critical patent/JP5144294B2/ja
Priority to TW097146558A priority patent/TW200939439A/zh
Priority to KR1020080127219A priority patent/KR20090086148A/ko
Publication of JP2009188150A publication Critical patent/JP2009188150A/ja
Publication of JP2009188150A5 publication Critical patent/JP2009188150A5/ja
Application granted granted Critical
Publication of JP5144294B2 publication Critical patent/JP5144294B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2008025930A 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法 Active JP5144294B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008025930A JP5144294B2 (ja) 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法
TW097146558A TW200939439A (en) 2008-02-06 2008-12-01 Lead frame and manufacturing method of circuit device using the lead frame
KR1020080127219A KR20090086148A (ko) 2008-02-06 2008-12-15 리드 프레임 및 그것을 이용한 회로 장치의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008025930A JP5144294B2 (ja) 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009188150A JP2009188150A (ja) 2009-08-20
JP2009188150A5 JP2009188150A5 (enExample) 2011-05-19
JP5144294B2 true JP5144294B2 (ja) 2013-02-13

Family

ID=41071116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008025930A Active JP5144294B2 (ja) 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法

Country Status (3)

Country Link
JP (1) JP5144294B2 (enExample)
KR (1) KR20090086148A (enExample)
TW (1) TW200939439A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5215980B2 (ja) * 2009-10-30 2013-06-19 株式会社三井ハイテック 半導体装置の製造方法
JP5397195B2 (ja) * 2009-12-02 2014-01-22 日立化成株式会社 光半導体素子搭載用基板の製造方法、及び、光半導体装置の製造方法
JP5613463B2 (ja) * 2010-06-03 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
DE102015100025A1 (de) * 2015-01-05 2016-07-07 Osram Opto Semiconductors Gmbh Leiterrahmen
JP6695166B2 (ja) * 2016-02-23 2020-05-20 株式会社三井ハイテック リードフレーム、及び半導体パッケージの製造方法
JP6924411B2 (ja) * 2017-08-28 2021-08-25 大日本印刷株式会社 リードフレームおよび半導体装置の製造方法
JP7548871B2 (ja) * 2021-05-31 2024-09-10 Ｔｏｗａ株式会社 成形型、樹脂成形装置及び樹脂成形品の製造方法
TWI882639B (zh) * 2024-01-08 2025-05-01 大陸商蘇州震坤科技有限公司 減少切單時刀損耗的導線架結構

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077235A (ja) * 1999-09-06 2001-03-23 Mitsui High Tec Inc 半導体素子搭載用基板
JP3634757B2 (ja) * 2001-02-02 2005-03-30 株式会社三井ハイテック リードフレーム
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
JP2007294715A (ja) * 2006-04-26 2007-11-08 Renesas Technology Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20090086148A (ko) 2009-08-11
TW200939439A (en) 2009-09-16
JP2009188150A (ja) 2009-08-20

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