JPWO2010150365A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JPWO2010150365A1 JPWO2010150365A1 JP2011519425A JP2011519425A JPWO2010150365A1 JP WO2010150365 A1 JPWO2010150365 A1 JP WO2010150365A1 JP 2011519425 A JP2011519425 A JP 2011519425A JP 2011519425 A JP2011519425 A JP 2011519425A JP WO2010150365 A1 JPWO2010150365 A1 JP WO2010150365A1
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Abstract
Description
さらに、本発明の半導体装置の製造方法は、電極パッドを有する半導体素子を準備する工程と、前記半導体素子より大きい面積の金属薄膜を準備し、前記半導体素子を前記金属薄膜上に、前記金属薄膜と電気的に絶縁して固定する工程と、前記電極パッドと前記金属薄膜とを接続部材により電気的に接続する工程と、前記金属薄膜上に前記半導体素子および前記接続部材を覆う絶縁層を形成する工程と、前記金属薄膜を所定形状の薄膜端子に形成する工程と、をこの工程の順に行うことを特徴とする。
以下、この発明の半導体装置の第1の実施形態について説明する。
図1は、本発明の半導体装置の拡大斜視図である。半導体装置10は、半導体素子11の下面に、分離部16で分離された複数の薄膜端子30Aを有する。半導体素子11は、集積回路が形成された半導体ウエハをダイシングすることにより得られる。半導体素子11は、表面が露出された複数の電極パッド12を有する。電極パッド12の周囲には、図示はしないが、酸化シリコン、あるいは、さらにその上にポリイミド膜等の保護膜が形成されている。図1において、電極パッド12はバンプ状とされているが、必ずしも、上面から突き出しておく必要はない。
なお、図1の半導体装置10は、半導体素子11の電極パッド12および薄膜端子30Aを、それぞれ、4個有する例として図示されているが、これは、図示の都合であって、実際には、半導体素子11の上面に多数の電極パッド12が形成され、半導体素子11の下面側には、電極パッド20に対応する数の薄膜端子30Aが形成されている。
各薄膜端子30Aは、変形部20を有する。図15は変形部20の拡大断面図である。
変形部20は、樹脂層15に対向する面側から外面側(換言すれば、図15の上面側から下面側)に向かって突き出されており、大略、外形が半球形状とされ、その中央部に陥没部を有する形状を有する。
変形部20の中央部分は、上面21aが、変形部20の周囲の20aと同一面とされた平坦な接続部21を有しており、この接続部21を溝23の斜面部23bが支持している。接続部21の上面21aにおいて、前述のワイヤ13の一端がボンディングされる。2点鎖線は、ワイヤ13のボンディング状態を示す。
接続部21および溝23の斜面部23bは、外側からみると、円錐体形状の陥没部24を形成しており、後述するが、この陥没部24内に、外部端子に接続するための導電性の接続材料が充填される。
半導体装置10の外形サイズは、2〜5mm(長さ)×2〜5mm(幅)×0.3〜0.8mm(厚さ)とすることが可能であり、このように小さいサイズの半導体装置10を、生産効率および信頼性が高く、且つ、効率的に生産することが可能である。
以下、第1実施形態の半導体装置の製造方法の一例を説明する。
図9に図示される通り、基台41、絶縁層42、金属薄膜30が、この順に密着して積層される。
一例として、変形部20の高さHを30〜70μm、直径Dを200〜300μmとし、絶縁層42の厚さTを50〜200μmとすることができる。但し、上記したT>Hの条件付きである。
キャピラリ(図示せず)によりワイヤを加熱して、ワイヤの一端を球状に成形して、金属薄膜30の変形部20の接続部21にボンディングし、他端を電極パッド12にボンディングする。これにより、ワイヤ13により電極パッド12と金属薄膜30が電気的に接続される。
そして、図8に図示されるように、各半導体素子11の下面に位置する金属薄膜30を、ダイシングブレード51を用いて、行方向および列方向いずれの方向においても分離部16で分離されるように切断する。
また、薄膜端子は、極めて薄い厚さにすることができるので、これによっても低コスト化および一層の薄型化を図ることができる。
さらに、薄膜端子30Aに溝23を有する変形部20を設けているので、薄膜端子30Aと樹脂層15との固着力の向上を図ることができる。
回路基板60には、上面に接続端子61が形成されている。この接続端子61に半導体装置10の薄膜端子30Aを位置合わせして、半田等の接合材62により両部材を接合する。
薄膜端子30Aは変形部20の中央部に陥没部24が形成されており、接合材62は、この陥没部24内を充填し接合強度を強化する。接合材62は、接続端子61上に設けておいてもよいし、変形部20の突出部22の表面および陥没部24内に設けておいてもよい。
また、接合材62は、半田に限らず、銀ペースト等の導電性接続材料、面方向には絶縁性で厚さ方向のみ導電性を示す異方導電性接続材等を適用することも可能である。
第1の実施形態では、半導体装置10の各薄膜端子30Aには、ワイヤ13が接続される位置のみに変形部20が形成されている。しかし、各薄膜端子30Aに変形部20を多数個形成するようにしてもよい。
図21は、このような半導体装置70の拡大断面図である。この半導体装置70の各薄膜端子35Aには多数の変形部20が形成されている。各変形部20は第1の実施形態に示す構造を有しており、突出部22と接続部21とが、長手方向に沿って交互に配列されている。複数の変形部20の1つに、他端が電極パッド12に接続されたワイヤ13の一端が接続されている。変形部20は、図面に垂直な方向にも、多数個、複数列に配列されて形成されている。
以下、図17〜図21を参照して、図21に図示された半導体装置の製造方法の一例を説明する。
なお、第2の実施形態において、第1の実施形態と同一な部材は、同一の参照番号を付し、適宜、その説明を省略する。
そして、図21に図示されるように、各半導体素子11の中央部の下面に位置する金属薄膜35を、ダイシング等適宜な方法により除去する。この後、各半導体装置形成領域の境界部で樹脂層15および金属薄膜35を切断することにより、個別に分離された薄膜端子35Aを有する半導体装置70を得る。
加えて、第2の実施形態の半導体装置70の場合には、変形部20がワイヤ13を接続する部分以外にも多数個形成されているので、金属薄膜35と樹脂層15の固着力を一層高めることができる。
以下に、第1の実施形態および第2の実施形態に示された半導体装置の変形例を示す。
図22は、半導体装置10の変形例である半導体装置10Aを示す。半導体装置10Aが半導体装置10と異なる点は、半導体装置10Aでは、分離部16が薄膜端子30Aのみでなく、絶縁材43を貫通し、半導体素子11の下面部にまで達する構成とされている点である。
図22は、半導体装置10の変形例として図示されているが、図21に示した半導体装置70に対しても同様に、分離部16を半導体素子11の下部に達する深さとすることができる。
図23は、半導体装置70の変形例として図示されているが、半導体装置10に対しても同様に、分離部16を、絶縁材43に達するが半導体素子11には達しない深さとすることができる。
第1および第2の実施形態では、金属薄膜30または35を半導体素子11の電極パッド12にワイヤ13により接続した後、金属薄膜30または35をダイシングブレードにより切断して、薄膜端子30Aまたは35Aに形成する方法であった。図24に図示される方法では、半導体素子11を搭載する前に、金属薄膜36に変形部20と共に分離部16を形成しておく。分離部16は、半導体素子11の中央部を通る行方向および列方向に延出し、その長さは、形成される薄膜端子の外形サイズを超える位置に達する長さとする。
図25に図示された例では、半導体素子11を搭載する前に、金属薄膜37に変形部20と共に、搭載される半導体素子11の中央部に対応する位置に、半導体素子11の外形サイズよりも小さい外形サイズの開口部17を形成しておく。
そして、金属薄膜37に半導体素子11を固着し、変形部20の接続部21と電極パッド12をワイヤで接続し、全体を樹脂層で覆った後、二点差線で示すように、開口部17を通過する行方向および列方向に沿って金属薄膜37を除去し、分離部16を形成する。これにより、金属薄膜37が個々に分離される。
この後、金属薄膜37および樹脂層を外形サイズで切断すれば、個々の半導体装置が得られる。
図26は、本発明の半導体装置の第3の実施形態を示す。この実施形態の半導体装置80は、薄膜端子が半導体素子11の全側辺部に沿って配列された例を示しており、図26(A)は上面図、図26(B)は図26(A)のXXVIB−XXVIB線切断断面図であり、図26(C)は、下面図である。
この実施形態における半導体素子11は、四辺のすべての側辺部に沿って配列された電極パッド12を有する。また、薄膜端子38Aも接続されるべき電極パッド12が配置された側辺部と同一の側辺部に配列されている。
図26では、電極パッド12および薄膜端子38Aは各側辺部に3個づつ配置されているが、各側辺部に配置される電極パッド12および薄膜端子38Aの数は、アライメントおよび薄膜端子形成時の解像度の限界まで増大することが可能であり、この点に関する本発明の適用可能性に制限はない。
半導体素子として、集積回路を有する集積回路素子を例として説明した。
しかし、この発明は、LED、ネットワーク用受動素子、半導体センサ等、ディスクリート部品や受動部品あるいはハイブリッド部品にも適用することができる。
11 半導体素子
12 電極パッド
13 ワイヤ(接続部材)
15 樹脂層
16 分離部
17 開口部
20 変形部
20a、21a 上面
21 接続部
22 突出部
23 溝
23a 最深部
24 陥没部
30、35、36、37 金属薄膜
30A、35A、36A、38A 薄膜端子
31 上面
41 基台
42 絶縁層
43 絶縁材
70、70A、80 半導体装置
Claims (16)
- 上面に複数の電極パッドを有する半導体素子と、
前記半導体素子の下面に、それぞれ、分離部にて分離して設けられた複数の薄膜端子と、
前記半導体素子および前記各薄膜端子との間に設けられた絶縁層と、
前記各半導体素子の電極パッドと前記各薄膜端子とを接続する接続部材と、
前記半導体素子、前記半導体素子から露出した前記複数の薄膜端子、前記分離部上および前記接続部材を覆って設けられた樹脂層と、
を具備することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、前記各薄膜端子は、前記樹脂層との接面側に微細な凹凸を有することを特徴とする半導体装置。
- 請求項1または請求項2のいずれか1項に記載の半導体装置において、前記薄膜端子は、前記樹脂層との対面側から外面側に突き出す変形部を有し、前記変形部内に前記樹脂層の一部が充填されていることを特徴とする半導体装置。
- 請求項3に記載の半導体装置において、前記接続部材の一端が前記薄膜端子に接続される接続部が前記薄膜端子の変形部内に形成されていることを特徴とする半導体装置。
- 請求項4に記載の半導体装置において、前記接続部は前記薄膜端子と一体に形成され、前記変形部の最深部よりも浅い位置に設けられていることを特徴とする半導体装置。
- 請求項4に記載の半導体装置において、前記薄膜端子は、前記半導体素子の下面に積層される領域と前記半導体素子の外側の領域とを有し、前記変形部は、前記薄膜端子の前記半導体素子の外側の領域に形成されていることを特徴とする半導体装置。
- 請求項1乃至請求項6のいずれか1項に記載の半導体装置において、前記変形部は前記接続部材よりも多く形成されていることを特徴とする半導体装置。
- 請求項1乃至請求項7のいずれか1項に記載の半導体装置において、前記薄膜端子は、厚さ30〜200μmであることを特徴とする半導体装置。
- 電極パッドを有する半導体素子を準備する工程と、
前記半導体素子より大きい面積の金属薄膜を準備し、前記半導体素子を前記金属薄膜上に、前記金属薄膜と電気的に絶縁して固定する工程と、
前記電極パッドと前記金属薄膜とを接続部材により電気的に接続する工程と、
前記金属薄膜上に前記半導体素子および前記接続部材を覆う絶縁層を形成する工程と、
前記金属薄膜を所定形状の薄膜端子に形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、前記金属薄膜を準備する工程は、前記半導体素子に対応する領域に開口部を形成する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項10に記載の半導体装置の製造方法において、前記開口部は前記半導体素子に対応しない領域に延出された部分を有することを特徴とする半導体装置の製造方法。
- 請求項9乃至請求項11のいずれかに記載の半導体装置の製造方法において、前記金属薄膜を準備する工程は、前記金属薄膜に前記樹脂膜との対面側から外面に向かって突き出す変形部を形成する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項12に記載の半導体装置の製造方法において、前記半導体素子より大きい面積の金属薄膜を準備する工程は、前記絶縁層を介して基台上に前記金属薄膜を接着する工程を含み、前記金属薄膜に前記変形部を形成する工程は、前記金属薄膜を前記絶縁層の内部に形成する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項請求項13に記載の半導体装置の製造方法において、前記絶縁層を介して基台上に前記金属薄膜を接着する工程は、前記変形部内に前記絶縁層を充填する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項13または請求項14のいずれか1項に記載の半導体装置の製造方法において、前記金属薄膜上に前記半導体素子および前記接続部材を覆う絶縁膜を形成する工程の後、前記金属薄膜を所定形状の薄膜端子に形成する工程の前に、前記基台を除去する工程を含むことを特徴とする半導体装置の製造方法。
- 電極パッドを有する半導体素子を準備する工程と、
前記半導体素子より大きい面積の金属薄膜を準備し、前記半導体素子を前記金属薄膜上に、前記金属薄膜と電気的に絶縁して固定する工程と、
前記電極パッドと前記金属薄膜とを接続部材により電気的に接続する工程と、
前記金属薄膜上に前記半導体素子および前記接続部材を覆う絶縁層を形成する工程と、
前記金属薄膜を所定形状の薄膜端子に形成する工程と、
をこの工程の順に行うことを特徴とする半導体装置の製造方法。
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