JP5094323B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP5094323B2
JP5094323B2 JP2007267562A JP2007267562A JP5094323B2 JP 5094323 B2 JP5094323 B2 JP 5094323B2 JP 2007267562 A JP2007267562 A JP 2007267562A JP 2007267562 A JP2007267562 A JP 2007267562A JP 5094323 B2 JP5094323 B2 JP 5094323B2
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JP
Japan
Prior art keywords
insulating layer
pad
opening
layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007267562A
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English (en)
Japanese (ja)
Other versions
JP2009099649A (ja
JP2009099649A5 (enExample
Inventor
裕司 雪入
泉 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007267562A priority Critical patent/JP5094323B2/ja
Priority to TW097139176A priority patent/TWI435676B/zh
Priority to KR1020080100736A priority patent/KR101477211B1/ko
Priority to US12/250,755 priority patent/US8196296B2/en
Publication of JP2009099649A publication Critical patent/JP2009099649A/ja
Publication of JP2009099649A5 publication Critical patent/JP2009099649A5/ja
Priority to US13/399,446 priority patent/US20120144666A1/en
Priority to US13/457,188 priority patent/US8561293B2/en
Application granted granted Critical
Publication of JP5094323B2 publication Critical patent/JP5094323B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49227—Insulator making

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007267562A 2007-10-15 2007-10-15 配線基板の製造方法 Active JP5094323B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2007267562A JP5094323B2 (ja) 2007-10-15 2007-10-15 配線基板の製造方法
TW097139176A TWI435676B (zh) 2007-10-15 2008-10-13 佈線板之製造方法
KR1020080100736A KR101477211B1 (ko) 2007-10-15 2008-10-14 배선 기판의 제조 방법
US12/250,755 US8196296B2 (en) 2007-10-15 2008-10-14 Method for manufacturing wiring board
US13/399,446 US20120144666A1 (en) 2007-10-15 2012-02-17 Method for manufacturing wiring board
US13/457,188 US8561293B2 (en) 2007-10-15 2012-04-26 Method for manufacturing wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007267562A JP5094323B2 (ja) 2007-10-15 2007-10-15 配線基板の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012202881A Division JP5479551B2 (ja) 2012-09-14 2012-09-14 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009099649A JP2009099649A (ja) 2009-05-07
JP2009099649A5 JP2009099649A5 (enExample) 2010-10-14
JP5094323B2 true JP5094323B2 (ja) 2012-12-12

Family

ID=40561998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007267562A Active JP5094323B2 (ja) 2007-10-15 2007-10-15 配線基板の製造方法

Country Status (4)

Country Link
US (3) US8196296B2 (enExample)
JP (1) JP5094323B2 (enExample)
KR (1) KR101477211B1 (enExample)
TW (1) TWI435676B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100704919B1 (ko) * 2005-10-14 2007-04-09 삼성전기주식회사 코어층이 없는 기판 및 그 제조 방법
US7344917B2 (en) * 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
KR101103301B1 (ko) * 2009-12-10 2012-01-11 엘지이노텍 주식회사 다층인쇄회로기판 및 그 제조방법
US8541693B2 (en) * 2010-03-31 2013-09-24 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
CN102340927A (zh) * 2010-07-27 2012-02-01 南亚电路板股份有限公司 印刷电路板
US8745860B2 (en) * 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP5385967B2 (ja) * 2011-12-22 2014-01-08 イビデン株式会社 配線板及びその製造方法
US20130241058A1 (en) * 2012-03-16 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wire Bonding Structures for Integrated Circuits
US10098242B2 (en) 2012-03-29 2018-10-09 Taiwan Green Point Enterprises Co., Ltd. Double-sided circuit board and method for preparing the same
JP6208411B2 (ja) * 2012-06-15 2017-10-04 新光電気工業株式会社 配線基板及びその製造方法
KR101412225B1 (ko) * 2012-08-10 2014-06-25 이비덴 가부시키가이샤 배선판 및 그 제조 방법
JP2015035496A (ja) * 2013-08-09 2015-02-19 イビデン株式会社 電子部品内蔵配線板の製造方法
JP6761224B2 (ja) * 2014-02-19 2020-09-23 味の素株式会社 プリント配線板、半導体装置及び樹脂シートセット
CN106356355B (zh) * 2015-07-15 2020-06-26 恒劲科技股份有限公司 基板结构及其制作方法
JP7320768B2 (ja) * 2016-01-26 2023-08-04 パナソニックＩｐマネジメント株式会社 樹脂付き金属箔、フレキシブルプリント配線板
JP2017228640A (ja) * 2016-06-22 2017-12-28 イビデン株式会社 プリント配線板の製造方法
CN107978586B (zh) * 2016-10-25 2019-11-26 上海新昇半导体科技有限公司 校准晶片及其制造方法
JP6915659B2 (ja) * 2017-12-06 2021-08-04 味の素株式会社 樹脂シート
WO2022003819A1 (ja) * 2020-06-30 2022-01-06 ギガフォトン株式会社 レーザ加工方法及び回路基板製造方法
WO2022070389A1 (ja) * 2020-10-01 2022-04-07 昭和電工マテリアルズ株式会社 配線基板の製造方法、半導体装置の製造方法、及び樹脂シート
FR3133482B1 (fr) * 2022-03-11 2025-02-28 St Microelectronics Grenoble 2 Substrat d’interconnexion et procédé de fabrication d’un tel substrat

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JPS62291087A (ja) 1986-06-10 1987-12-17 日立化成工業株式会社 配線板の製造方法
JPH06304774A (ja) * 1993-04-23 1994-11-01 Murata Mfg Co Ltd 積層型セラミック電子部品の製造方法
JP3395621B2 (ja) * 1997-02-03 2003-04-14 イビデン株式会社 プリント配線板及びその製造方法
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JP2000022337A (ja) * 1998-06-30 2000-01-21 Matsushita Electric Works Ltd 多層配線板及びその製造方法
JP3670487B2 (ja) 1998-06-30 2005-07-13 京セラ株式会社 配線基板の製造方法
JP2000244115A (ja) * 1999-02-17 2000-09-08 Ibiden Co Ltd プリント配線板の製造方法
ATE222046T1 (de) * 1999-03-23 2002-08-15 Circuit Foil Luxembourg Trading Sarl Verfahren zur herstellung einer mehrschichtigen gedruckten leiterplatte und verbundfolie zur verwendung darin
JP2004241394A (ja) * 2000-02-08 2004-08-26 Ajinomoto Co Inc 接着フィルム及びこれを用いた積層板の製造法
JP2001308536A (ja) * 2000-04-27 2001-11-02 Kyocera Corp 多層配線基板およびその製造方法
JP2002324974A (ja) * 2001-04-24 2002-11-08 Sony Corp 多層プリント配線基板及び多層プリント配線基板の製造方法
JP3992524B2 (ja) 2002-03-29 2007-10-17 住友ベークライト株式会社 多層配線板およびその製造方法ならびに半導体装置
JP2006203074A (ja) * 2005-01-21 2006-08-03 Sumitomo Bakelite Co Ltd 回路基板の製造方法および回路基板
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JP4334005B2 (ja) 2005-12-07 2009-09-16 新光電気工業株式会社 配線基板の製造方法及び電子部品実装構造体の製造方法

Also Published As

Publication number Publication date
US20120204424A1 (en) 2012-08-16
US20120144666A1 (en) 2012-06-14
TWI435676B (zh) 2014-04-21
US20090100673A1 (en) 2009-04-23
JP2009099649A (ja) 2009-05-07
KR101477211B1 (ko) 2014-12-30
KR20090038375A (ko) 2009-04-20
TW200938044A (en) 2009-09-01
US8196296B2 (en) 2012-06-12
US8561293B2 (en) 2013-10-22

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