JP5090712B2 - フラッシュメモリ素子のプログラム方法 - Google Patents
フラッシュメモリ素子のプログラム方法 Download PDFInfo
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- JP5090712B2 JP5090712B2 JP2006301419A JP2006301419A JP5090712B2 JP 5090712 B2 JP5090712 B2 JP 5090712B2 JP 2006301419 A JP2006301419 A JP 2006301419A JP 2006301419 A JP2006301419 A JP 2006301419A JP 5090712 B2 JP5090712 B2 JP 5090712B2
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- 238000000034 method Methods 0.000 title claims description 36
- 230000008672 reprogramming Effects 0.000 claims description 14
- 238000012795 verification Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
102…セルストリング
110…ドレイン選択トランジスタ
120…ソース選択トランジスタ
201…セルストリング
202…セルストリング
210…ドレイン選択トランジスタ
220…ソース選択トランジスタ
301…セルストリング
302…セルストリング
310…ドレイン選択トランジスタ
320…ソース選択トランジスタ
401…セルストリング
402…セルストリング
410…ドレイン選択トランジスタ
420…ソース選択トランジスタ
Claims (15)
- 選択されたメモリセルに対してプログラム及びプログラム検証を実施する段階及び
前記プログラムされたセルが最後のワードラインに連結されたセルである場合、再プログラムを実施する段階を含むフラッシュメモリ素子のプログラム方法。 - 前記プログラムは、前記選択されたセルと連結されたワードラインに所定のプログラム電圧を印加し、選択されていないセルと連結されたワードラインに所定のパス電圧を印加して実施する請求項1に記載のフラッシュメモリ素子のプログラム方法。
- 前記プログラムは、前記選択されたセルと連結されたビットラインに接地電圧を印加し、前記選択されていないセルと連結されたビットラインに電源電圧を印加して実施する請求項1または2に記載のフラッシュメモリ素子のプログラム方法。
- 前記プログラム検証は、前記選択されたセルと連結されたワードラインに所定の検証電圧を印加し、前記選択されたセルと連結されていないワードラインに電源電圧を印加して実施する請求項1に記載のフラッシュメモリ素子のプログラム方法。
- 前記検証電圧は、前記電源電圧より低く印加する請求項4に記載のフラッシュメモリ素子のプログラム方法。
- 前記検証電圧は0〜1Vである請求項5に記載のフラッシュメモリ素子のプログラム方法。
- 前記プログラム検証は、前記選択されたセルと連結されたビットラインに前記電源電圧より低い電圧を印加し、前記選択されていないセルと連結されたビットラインに接地電圧を印加して実施する請求項1または4に記載のフラッシュメモリ素子のプログラム方法。
- 前記再プログラムは、前記最後のワードラインを通じて所定の再プログラム電圧を印加し、前記最後のワードライン以外のワードラインを通じて電源電圧を印加して実施する請求項1に記載のフラッシュメモリ素子のプログラム方法。
- 前記再プログラム電圧は、前記プログラム検証時の電圧より同一または高い電圧である請求項8に記載のフラッシュメモリ素子のプログラム方法。
- 前記再プログラム電圧は1〜1.5Vである請求項8に記載のフラッシュメモリ素子のプログラム方法。
- 前記再プログラムは、前記選択されたセルと連結されたビットラインには所定の電圧を印加し、前記選択されたセルと連結されていないビットラインには接地電圧を印加して実施する請求項1または8に記載のフラッシュメモリ素子のプログラム方法。
- 前記選択されたセルと連結されたビットラインに印加される電圧は前記電源電圧より高い電圧である請求項11に記載のフラッシュメモリ素子のプログラム方法。
- 前記選択されたセルと連結されたビットラインに印加される電圧は5Vである請求項11に記載のフラッシュメモリ素子のプログラム方法。
- 前記再プログラムは、150μs以下の時間実施する請求項1に記載のフラッシュメモリ素子のプログラム方法。
- 選択されたセルのワードラインを通じて所定のプログラム電圧を印加してプログラムを実施する段階、
前記プログラムを実施したセルのプログラム状態を検証する段階、
前記検証結果、プログラムされていないセルに対して前記プログラム電圧を上昇させてプログラムを反復実施する段階、及び
前記検証結果、プログラムされたセルが最後のワードラインに連結されたセルの場合、所定の再プログラム電圧を前記最後のワードラインを通じて印加し、ビットラインを通じて所定の電圧を印加して再プログラムする段階を含むフラッシュメモリ素子のプログラム方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2006-0041769 | 2006-05-10 | ||
KR1020060041769A KR100766241B1 (ko) | 2006-05-10 | 2006-05-10 | 플래쉬 메모리 소자의 프로그램 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007305281A JP2007305281A (ja) | 2007-11-22 |
JP5090712B2 true JP5090712B2 (ja) | 2012-12-05 |
Family
ID=38684940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006301419A Expired - Fee Related JP5090712B2 (ja) | 2006-05-10 | 2006-11-07 | フラッシュメモリ素子のプログラム方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7539061B2 (ja) |
JP (1) | JP5090712B2 (ja) |
KR (1) | KR100766241B1 (ja) |
CN (1) | CN100520979C (ja) |
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2006
- 2006-05-10 KR KR1020060041769A patent/KR100766241B1/ko not_active IP Right Cessation
- 2006-11-07 US US11/557,343 patent/US7539061B2/en not_active Expired - Fee Related
- 2006-11-07 US US11/557,337 patent/US7417899B2/en active Active
- 2006-11-07 JP JP2006301419A patent/JP5090712B2/ja not_active Expired - Fee Related
- 2006-11-24 CN CNB2006101452726A patent/CN100520979C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2007305281A (ja) | 2007-11-22 |
US7417899B2 (en) | 2008-08-26 |
KR100766241B1 (ko) | 2007-10-10 |
US7539061B2 (en) | 2009-05-26 |
US20070263452A1 (en) | 2007-11-15 |
CN100520979C (zh) | 2009-07-29 |
US20070263451A1 (en) | 2007-11-15 |
CN101071642A (zh) | 2007-11-14 |
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