JP5080032B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP5080032B2 JP5080032B2 JP2006176107A JP2006176107A JP5080032B2 JP 5080032 B2 JP5080032 B2 JP 5080032B2 JP 2006176107 A JP2006176107 A JP 2006176107A JP 2006176107 A JP2006176107 A JP 2006176107A JP 5080032 B2 JP5080032 B2 JP 5080032B2
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- 239000004065 semiconductor Substances 0.000 title claims description 52
- 239000012535 impurity Substances 0.000 claims description 152
- 230000015556 catabolic process Effects 0.000 claims description 55
- 238000009792 diffusion process Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- 229910052787 antimony Inorganic materials 0.000 claims description 7
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 230000005684 electric field Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 description 21
- 230000006378 damage Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
2 第1のN型高濃度不純物領域
3 第1のN型低濃度不純物領域
4 第2のN型高濃度不純物領域
5 第2のN型低濃度不純物領域
6 第3のN型高濃度不純物領域
7 第3のN型低濃度不純物領域
8 ゲート絶縁膜
9 ゲート電極
10 厚い絶縁膜
11 接触深さ
101 第1のNチャネル型低耐圧MOSトランジスタ
102 第1のNチャネル型高耐圧MOSトランジスタ
103 第2のNチャネル型低耐圧MOSトランジスタ
Claims (8)
- 半導体基板表面に設けられた、第1のゲート絶縁膜と、第1のゲート電極と、第1のN型高濃度不純物領域および電界緩和のための第1のN型低濃度不純物領域からなる第1のソース・ドレイン領域とから構成されるNチャネル型の低耐圧MOSトランジスタと、
第2のゲート絶縁膜と、第2のゲート電極と、第2のN型高濃度不純物領域および電界緩和のための第2のN型低濃度不純物領域からなる第2のソース・ドレイン領域と、前記第2のゲート絶縁膜より厚い、前記第2の低濃度不純物領域上に形成された絶縁膜とから構成されるNチャネル型の高耐圧MOSトランジスタと、
を含む半導体集積回路装置であって、
前記第2のN型高濃度不純物領域を構成する不純物の拡散係数は前記第1のN型高濃度不純物領域を構成する不純物の拡散係数よりも大きく、前記第2のN型高濃度不純物領域の前記半導体基板表面からの拡散深さは前記第2のN型低濃度不純物領域の前記半導体基板表面からの拡散深さより深く、前記第2のN型低濃度不純物領域の前記半導体基板表面からの拡散深さは前記第2のN型高濃度不純物領域と前記第2のN型低濃度不純物領域とが接触して交わっている深さ方向の長さである接触深さより深いことを特徴とする半導体集積回路装置。 - 半導体基板表面に設けられた、第1のゲート絶縁膜と、第1のゲート電極と、第1のN型高濃度不純物領域および電界緩和のための第1のN型低濃度不純物領域からなる第1のソース・ドレイン領域とから構成される第1のNチャネル型の低耐圧MOSトランジスタと、
第2のゲート絶縁膜と、第2のゲート電極と、第2のN型高濃度不純物領域および電界緩和のための第2のN型低濃度不純物領域からなる第2のソース・ドレイン領域と、前記第2のゲート絶縁膜より厚い、前記第2の低濃度不純物領域上に形成された絶縁膜とから構成されるNチャネル型の高耐圧MOSトランジスタと、
第3のゲート絶縁膜と、第3のゲート電極と、第3のN型高濃度不純物領域とから構成される第2のNチャネル型の低耐圧MOSトランジスタと、
を含む半導体集積回路装置であって、
前記第2のN型高濃度不純物領域および前記第3のN型高濃度不純物領域を構成する不純物の拡散係数は前記第1のN型高濃度不純物領域を構成する不純物の拡散係数よりも大きく、前記第2のN型高濃度不純物領域の前記半導体基板表面からの拡散深さは前記第2のN型低濃度不純物領域の前記半導体基板表面からの拡散深さより深く、前記第2のN型低濃度不純物領域の前記半導体基板表面からの拡散深さは前記第2のN型高濃度不純物領域と前記第2のN型低濃度不純物領域とが接触して交わっている深さ方向の長さである接触深さより深いことを特徴とする半導体集積回路装置。 - 前記第1のN型高濃度不純物領域を構成する不純物はヒ素で、前記第2の高濃度不純物領域を構成する不純物はリンであることを特徴とする請求項1記載の半導体集積回路装置。
- 前記第1のN型高濃度不純物領域を構成する不純物はアンチモンで、前記第2の高濃度不純物領域を構成する不純物はリンであることを特徴とする請求項1記載の半導体集積回路装置。
- 前記第1のN型高濃度不純物領域を構成する不純物はヒ素で、前記第2の高濃度不純物領域および前記第3のN型高濃度不純物領域を構成する不純物はリンであることを特徴とする請求項2記載の半導体集積回路装置。
- 前記第1のN型高濃度不純物領域を構成する不純物はアンチモンで、前記第2の高濃度不純物領域および前記第3のN型高濃度不純物領域を構成する不純物はリンであることを特徴とする請求項2記載の半導体集積回路装置。
- 前記第2の高濃度不純物濃度が1×1019/cm3以上で深さが0.5μm以上であり、前記第2の低濃度不純物濃度が1×1017から5×1017/cm3の濃度であり深さが0.3μm以下であることを特徴とする請求項2記載の半導体集積回路装置。
- 前記第2の高濃度不純物領域と前記第2の低濃度不純物濃度の接触深さが0.2μm以上であることを特徴とする請求項2記載の半導体集積回路装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006176107A JP5080032B2 (ja) | 2006-06-27 | 2006-06-27 | 半導体集積回路装置 |
US11/823,273 US7750411B2 (en) | 2006-06-27 | 2007-06-26 | Semiconductor integrated circuit device |
CN2007101096957A CN101097920B (zh) | 2006-06-27 | 2007-06-27 | 半导体集成电路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006176107A JP5080032B2 (ja) | 2006-06-27 | 2006-06-27 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008010443A JP2008010443A (ja) | 2008-01-17 |
JP5080032B2 true JP5080032B2 (ja) | 2012-11-21 |
Family
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JP2006176107A Expired - Fee Related JP5080032B2 (ja) | 2006-06-27 | 2006-06-27 | 半導体集積回路装置 |
Country Status (3)
Country | Link |
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US (1) | US7750411B2 (ja) |
JP (1) | JP5080032B2 (ja) |
CN (1) | CN101097920B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5324849B2 (ja) * | 2008-07-18 | 2013-10-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5449942B2 (ja) * | 2009-09-24 | 2014-03-19 | セイコーインスツル株式会社 | 半導体装置およびその製造方法 |
JP5630185B2 (ja) * | 2010-09-30 | 2014-11-26 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP6700648B2 (ja) * | 2012-10-18 | 2020-05-27 | 富士電機株式会社 | 半導体装置の製造方法 |
JP6595872B2 (ja) | 2015-02-25 | 2019-10-23 | エイブリック株式会社 | 半導体集積回路装置およびその製造方法 |
JP7009033B2 (ja) * | 2018-02-06 | 2022-01-25 | エイブリック株式会社 | 基準電圧発生装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52106279A (en) * | 1976-03-03 | 1977-09-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor ic |
JPH0258274A (ja) * | 1988-08-23 | 1990-02-27 | Seiko Epson Corp | 半導体装置 |
JPH03225952A (ja) * | 1990-01-31 | 1991-10-04 | Sanyo Electric Co Ltd | 半導体集積回路 |
JP3592734B2 (ja) | 1993-06-08 | 2004-11-24 | 富士電機デバイステクノロジー株式会社 | Mos型電界効果トランジスタおよびその製造方法 |
KR970013402A (ko) * | 1995-08-28 | 1997-03-29 | 김광호 | 플래쉬 메모리장치 및 그 제조방법 |
JP3270405B2 (ja) * | 1998-01-26 | 2002-04-02 | セイコーインスツルメンツ株式会社 | 半導体装置 |
JP4398010B2 (ja) * | 1999-06-16 | 2010-01-13 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
JP2002313946A (ja) * | 2001-04-12 | 2002-10-25 | Seiko Instruments Inc | 半導体装置 |
JP2002329728A (ja) * | 2001-05-02 | 2002-11-15 | Seiko Epson Corp | 高耐圧トランジスタ、半導体装置および高耐圧トランジスタの製造方法 |
JP3719189B2 (ja) * | 2001-10-18 | 2005-11-24 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
-
2006
- 2006-06-27 JP JP2006176107A patent/JP5080032B2/ja not_active Expired - Fee Related
-
2007
- 2007-06-26 US US11/823,273 patent/US7750411B2/en not_active Expired - Fee Related
- 2007-06-27 CN CN2007101096957A patent/CN101097920B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7750411B2 (en) | 2010-07-06 |
JP2008010443A (ja) | 2008-01-17 |
US20080006879A1 (en) | 2008-01-10 |
CN101097920B (zh) | 2012-09-05 |
CN101097920A (zh) | 2008-01-02 |
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