JP5070228B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5070228B2
JP5070228B2 JP2009010499A JP2009010499A JP5070228B2 JP 5070228 B2 JP5070228 B2 JP 5070228B2 JP 2009010499 A JP2009010499 A JP 2009010499A JP 2009010499 A JP2009010499 A JP 2009010499A JP 5070228 B2 JP5070228 B2 JP 5070228B2
Authority
JP
Japan
Prior art keywords
lsi
clock signal
flip
circuit
flops
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009010499A
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English (en)
Japanese (ja)
Other versions
JP2010171092A5 (https=
JP2010171092A (ja
Inventor
一雄 大津賀
健一 長田
真 佐圓
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2009010499A priority Critical patent/JP5070228B2/ja
Priority to US12/690,659 priority patent/US7994822B2/en
Publication of JP2010171092A publication Critical patent/JP2010171092A/ja
Publication of JP2010171092A5 publication Critical patent/JP2010171092A5/ja
Application granted granted Critical
Publication of JP5070228B2 publication Critical patent/JP5070228B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15033—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of bistable devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP2009010499A 2009-01-21 2009-01-21 半導体装置 Expired - Fee Related JP5070228B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009010499A JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置
US12/690,659 US7994822B2 (en) 2009-01-21 2010-01-20 Semiconductor device for synchronous communication between stacked LSI

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009010499A JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置

Publications (3)

Publication Number Publication Date
JP2010171092A JP2010171092A (ja) 2010-08-05
JP2010171092A5 JP2010171092A5 (https=) 2011-10-20
JP5070228B2 true JP5070228B2 (ja) 2012-11-07

Family

ID=42336451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009010499A Expired - Fee Related JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置

Country Status (2)

Country Link
US (1) US7994822B2 (https=)
JP (1) JP5070228B2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8179173B2 (en) * 2010-03-12 2012-05-15 Raytheon Company Digitally calibrated high speed clock distribution
US8384435B2 (en) * 2011-01-05 2013-02-26 Texas Instruments Incorporated Clock switching circuit with priority multiplexer
JP5643665B2 (ja) * 2011-01-24 2014-12-17 学校法人慶應義塾 積層型半導体集積回路装置
JP5643673B2 (ja) * 2011-02-16 2014-12-17 学校法人慶應義塾 電子回路
US8786080B2 (en) * 2011-03-11 2014-07-22 Altera Corporation Systems including an I/O stack and methods for fabricating such systems
JP5807550B2 (ja) 2012-01-10 2015-11-10 株式会社ソシオネクスト 半導体装置
JP6312377B2 (ja) * 2013-07-12 2018-04-18 キヤノン株式会社 半導体装置
US9231603B2 (en) 2014-03-31 2016-01-05 International Business Machines Corporation Distributed phase detection for clock synchronization in multi-layer 3D stacks
US10147658B2 (en) 2014-06-09 2018-12-04 SK Hynix Inc. Stacked semiconductor apparatus being electrically connected through through-via and monitoring method
KR20150141018A (ko) * 2014-06-09 2015-12-17 에스케이하이닉스 주식회사 관통 비아를 통해 연결되는 적층 반도체 장치 및 모니터링 방법
US9319829B1 (en) * 2014-10-30 2016-04-19 Hua Wen Hsu Wireless inductive pointer clock
JP2017163204A (ja) * 2016-03-07 2017-09-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 通信装置
KR102605617B1 (ko) 2016-11-10 2023-11-23 삼성전자주식회사 적층 반도체 패키지
KR20230071383A (ko) 2021-11-16 2023-05-23 삼성전자주식회사 반도체 장치, 반도체 패키지 및 메모리 시스템
US12578753B2 (en) 2023-01-27 2026-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Clock aligning circuit and methods for operating the same
US20250370497A1 (en) * 2024-05-31 2025-12-04 Ati Technologies Ulc Chiplet clock forwarding architecture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4063392B2 (ja) * 1998-03-26 2008-03-19 富士通株式会社 信号伝送システム
JP3475857B2 (ja) * 1999-06-03 2003-12-10 日本電気株式会社 ソースシンクロナス転送方式
JP2001251283A (ja) * 2000-03-06 2001-09-14 Hitachi Ltd インターフェース回路
US6331800B1 (en) * 2000-07-21 2001-12-18 Hewlett-Packard Company Post-silicon methods for adjusting the rise/fall times of clock edges
JP4752369B2 (ja) * 2004-08-24 2011-08-17 ソニー株式会社 半導体装置および基板
JP5063958B2 (ja) 2006-08-18 2012-10-31 川崎マイクロエレクトロニクス株式会社 半導体集積回路および半導体集積回路の設計方法
JP5149554B2 (ja) 2007-07-17 2013-02-20 株式会社日立製作所 半導体装置
JP2009032857A (ja) 2007-07-26 2009-02-12 Hitachi Ltd 半導体集積回路および半導体装置
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
JP5258343B2 (ja) 2008-03-27 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置及び半導体集積回路

Also Published As

Publication number Publication date
US20100182046A1 (en) 2010-07-22
JP2010171092A (ja) 2010-08-05
US7994822B2 (en) 2011-08-09

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