JP5069449B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5069449B2
JP5069449B2 JP2006308322A JP2006308322A JP5069449B2 JP 5069449 B2 JP5069449 B2 JP 5069449B2 JP 2006308322 A JP2006308322 A JP 2006308322A JP 2006308322 A JP2006308322 A JP 2006308322A JP 5069449 B2 JP5069449 B2 JP 5069449B2
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JP
Japan
Prior art keywords
layer
wiring
substrate
pad
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006308322A
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English (en)
Japanese (ja)
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JP2008124339A (ja
JP2008124339A5 (enExample
Inventor
泰彦 草間
茂次 村松
正宏 経塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2006308322A priority Critical patent/JP5069449B2/ja
Publication of JP2008124339A publication Critical patent/JP2008124339A/ja
Publication of JP2008124339A5 publication Critical patent/JP2008124339A5/ja
Application granted granted Critical
Publication of JP5069449B2 publication Critical patent/JP5069449B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2006308322A 2006-11-14 2006-11-14 配線基板及びその製造方法 Active JP5069449B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006308322A JP5069449B2 (ja) 2006-11-14 2006-11-14 配線基板及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006308322A JP5069449B2 (ja) 2006-11-14 2006-11-14 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2008124339A JP2008124339A (ja) 2008-05-29
JP2008124339A5 JP2008124339A5 (enExample) 2009-11-05
JP5069449B2 true JP5069449B2 (ja) 2012-11-07

Family

ID=39508751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006308322A Active JP5069449B2 (ja) 2006-11-14 2006-11-14 配線基板及びその製造方法

Country Status (1)

Country Link
JP (1) JP5069449B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110038521A (ko) * 2009-10-08 2011-04-14 엘지이노텍 주식회사 인쇄회로기판 및 그 제조방법
KR20180037238A (ko) * 2015-08-28 2018-04-11 히타치가세이가부시끼가이샤 반도체 장치 및 그 제조 방법
KR102631808B1 (ko) * 2017-05-19 2024-01-31 베지 사사키 전자 부품 탑재용 기판 및 그 제조 방법
TWI705747B (zh) * 2019-08-30 2020-09-21 嘉聯益科技股份有限公司 多層軟性電路板及其製造方法
JP2022014750A (ja) * 2020-07-07 2022-01-20 キオクシア株式会社 半導体装置およびその製造方法
TWI831123B (zh) * 2022-01-28 2024-02-01 巨擘科技股份有限公司 多層基板表面處理層結構
CN115190701B (zh) * 2022-05-13 2023-06-02 广州广芯封装基板有限公司 一种埋入式线路封装基板及其加工方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253091A (ja) * 1990-03-02 1991-11-12 Tokuyama Soda Co Ltd プリント配線板の製造方法
JPH11126974A (ja) * 1997-10-24 1999-05-11 Asahi Chem Res Lab Ltd 多層配線板の製造方法
JP2002299779A (ja) * 2001-03-30 2002-10-11 Hitachi Metals Ltd 配線形成用帯材及びそれを用いたバンプ付き配線を有する配線板並びに配線形成用帯材を用いた転写配線板の製造方法
JP2003008228A (ja) * 2001-06-22 2003-01-10 Ibiden Co Ltd 多層プリント配線板およびその製造方法
JP2004095972A (ja) * 2002-09-03 2004-03-25 Sumitomo Metal Electronics Devices Inc プラスチックパッケージの製造方法
JP2005166910A (ja) * 2003-12-02 2005-06-23 Fujikura Ltd プリント配線板およびその製造方法

Also Published As

Publication number Publication date
JP2008124339A (ja) 2008-05-29

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