JP5049733B2 - 情報処理システム - Google Patents
情報処理システム Download PDFInfo
- Publication number
- JP5049733B2 JP5049733B2 JP2007269772A JP2007269772A JP5049733B2 JP 5049733 B2 JP5049733 B2 JP 5049733B2 JP 2007269772 A JP2007269772 A JP 2007269772A JP 2007269772 A JP2007269772 A JP 2007269772A JP 5049733 B2 JP5049733 B2 JP 5049733B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- memory cell
- control circuit
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/10—Resistive cells; Technology aspects
- G11C2213/11—Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/34—Material includes an oxide or a nitride
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Memory System (AREA)
- Dram (AREA)
Description
[全体構成]
図1は、本発明の第1の実施の形態に係る情報処理システムであるコンピュータシステムの構成を示すブロック図である。
図2は、メインメモリ20に使用される不揮発性メモリ22のブロック図である。
図3は、メモリセルアレイ1の一部の斜視図、図4は、図3におけるI−I′線で切断して矢印方向に見たメモリセル1つ分の断面図である。
次に、このように構成されたコンピュータシステムにおける不揮発性半導体メモリの動作について説明する。
上記第1の実施形態では、リフレッシュ動作をページ毎に読み出し、消去及び書き込みの順に行った。この場合、データを元の記憶場所に完全に書き直すだけであり、FATの変更等は必要ない。
図16は、本発明の第3の実施形態に係る大容量カードシステムの構成を示すブロック図である。先の実施形態では、抵抗変化型不揮発性メモリ22をコンピュータシステムのメインメモリ20に使用し、リフレッシュ命令は、コンピュータシステムのCPU10から発行されていた。
図17は、本発明の第4の実施形態に係る不揮発性半導体記憶装置のリフレッシュ動作を説明するためのメモリの構成を示す図である。
Claims (3)
- データを記憶するメインメモリと、
このメインメモリに対してデータをアクセスする制御回路とを有し、
前記メインメモリは、
可変抵抗素子を使用した電気的に書き換え可能な不揮発性のメモリセルを複数配列してなるメモリセルアレイを有し、当該メモリセルアレイが独立にアクセス可能な複数の分割単位で分割されている不揮発性半導体記憶装置と、
前記制御回路と前記不揮発性半導体記憶装置との間にキャッシュメモリとして配置されるDRAMと
を備え、
前記制御回路は、前記メモリセルアレイから前記分割単位毎に1メモリセルずつ並列にアクセスし、当該アクセス単位で記憶されたデータを再書き込みするリフレッシュモードを実行する
ことを特徴とする情報処理システム。 - 前記制御回路は、前記不揮発性半導体記憶装置に対するアクセス回数に基づいて前記不揮発性半導体記憶装置のリフレッシュモードを起動する
ことを特徴とする請求項1記載の情報処理システム。 - 前記不揮発性半導体記憶装置は、前記リフレッシュモード時に、前記アクセス単位のデータを一括読み出しし、前記アクセス単位に前記読み出したデータを再度書き込む
ことを特徴とする請求項1又は2記載の情報処理システム。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007269772A JP5049733B2 (ja) | 2007-10-17 | 2007-10-17 | 情報処理システム |
CN201310603463.2A CN103594115A (zh) | 2007-10-17 | 2008-10-17 | 信息处理系统 |
US12/672,083 US20100211725A1 (en) | 2007-10-17 | 2008-10-17 | Information processing system |
KR1020107003299A KR20100044213A (ko) | 2007-10-17 | 2008-10-17 | 정보 처리 시스템 |
PCT/JP2008/069287 WO2009051276A1 (en) | 2007-10-17 | 2008-10-17 | Information processing system |
EP08840090A EP2198428A4 (en) | 2007-10-17 | 2008-10-17 | INFORMATION PROCESSING SYSTEM |
CN2008801116987A CN101828234B (zh) | 2007-10-17 | 2008-10-17 | 信息处理系统 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007269772A JP5049733B2 (ja) | 2007-10-17 | 2007-10-17 | 情報処理システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009099200A JP2009099200A (ja) | 2009-05-07 |
JP5049733B2 true JP5049733B2 (ja) | 2012-10-17 |
Family
ID=40567530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007269772A Expired - Fee Related JP5049733B2 (ja) | 2007-10-17 | 2007-10-17 | 情報処理システム |
Country Status (6)
Country | Link |
---|---|
US (1) | US20100211725A1 (ja) |
EP (1) | EP2198428A4 (ja) |
JP (1) | JP5049733B2 (ja) |
KR (1) | KR20100044213A (ja) |
CN (2) | CN103594115A (ja) |
WO (1) | WO2009051276A1 (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5426438B2 (ja) * | 2009-04-30 | 2014-02-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR101097435B1 (ko) | 2009-06-15 | 2011-12-23 | 주식회사 하이닉스반도체 | 멀티 레벨을 갖는 상변화 메모리 장치 및 그 구동방법 |
US8626997B2 (en) * | 2009-07-16 | 2014-01-07 | Micron Technology, Inc. | Phase change memory in a dual inline memory module |
JP5281163B2 (ja) * | 2009-08-21 | 2013-09-04 | 株式会社日立製作所 | 半導体装置およびメモリモジュール |
JP5482021B2 (ja) * | 2009-08-26 | 2014-04-23 | 富士通株式会社 | 抵抗スイッチ素子および抵抗スイッチメモリ素子 |
JP5558090B2 (ja) * | 2009-12-16 | 2014-07-23 | 株式会社東芝 | 抵抗変化型メモリセルアレイ |
JP5346964B2 (ja) * | 2011-02-02 | 2013-11-20 | 京セラドキュメントソリューションズ株式会社 | 電子機器およびシステム管理プログラム |
JP5277262B2 (ja) * | 2011-01-13 | 2013-08-28 | 京セラドキュメントソリューションズ株式会社 | 電子機器およびシステム管理プログラム |
US8612676B2 (en) | 2010-12-22 | 2013-12-17 | Intel Corporation | Two-level system main memory |
WO2013048493A1 (en) | 2011-09-30 | 2013-04-04 | Intel Corporation | Memory channel that supports near memory and far memory access |
JP2013110279A (ja) * | 2011-11-21 | 2013-06-06 | Toshiba Corp | 不揮発性記憶装置 |
JP2013161878A (ja) * | 2012-02-02 | 2013-08-19 | Renesas Electronics Corp | 半導体装置、および半導体装置の製造方法 |
KR101431215B1 (ko) * | 2012-12-04 | 2014-08-19 | 성균관대학교산학협력단 | 반도체 메모리 장치, 리프레쉬 방법 및 시스템 |
US9146882B2 (en) | 2013-02-04 | 2015-09-29 | International Business Machines Corporation | Securing the contents of a memory device |
JP5989611B2 (ja) | 2013-02-05 | 2016-09-07 | 株式会社東芝 | 半導体記憶装置、及びそのデータ制御方法 |
KR102092776B1 (ko) | 2013-11-20 | 2020-03-24 | 에스케이하이닉스 주식회사 | 전자 장치 |
US10116336B2 (en) * | 2014-06-13 | 2018-10-30 | Sandisk Technologies Llc | Error correcting code adjustment for a data storage device |
KR102151183B1 (ko) * | 2014-06-30 | 2020-09-02 | 삼성전자주식회사 | 저항성 메모리 장치 및 저항성 메모리 장치의 동작방법 |
JP6497393B2 (ja) * | 2014-10-31 | 2019-04-10 | ソニー株式会社 | メモリコントローラ、記憶装置、情報処理システムおよびメモリの制御方法 |
CN105808455B (zh) * | 2014-12-31 | 2020-04-28 | 华为技术有限公司 | 访问内存的方法、存储级内存及计算机系统 |
US9697874B1 (en) * | 2015-06-09 | 2017-07-04 | Crossbar, Inc. | Monolithic memory comprising 1T1R code memory and 1TnR storage class memory |
KR102559530B1 (ko) | 2016-09-19 | 2023-07-27 | 에스케이하이닉스 주식회사 | 저항성 메모리 장치, 이를 위한 디스터번스 방지 회로 및 방법 |
JP6697360B2 (ja) * | 2016-09-20 | 2020-05-20 | キオクシア株式会社 | メモリシステムおよびプロセッサシステム |
KR102658230B1 (ko) * | 2018-06-01 | 2024-04-17 | 삼성전자주식회사 | 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법 |
US11189662B2 (en) | 2018-08-13 | 2021-11-30 | Micron Technology | Memory cell stack and via formation for a memory device |
US11373695B2 (en) * | 2019-12-18 | 2022-06-28 | Micron Technology, Inc. | Memory accessing with auto-precharge |
US11139016B1 (en) | 2020-04-07 | 2021-10-05 | Micron Technology, Inc. | Read refresh operation |
US11404120B2 (en) | 2020-05-13 | 2022-08-02 | Micron Technology, Inc. | Refresh operation of a memory cell |
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JP4146006B2 (ja) * | 1998-09-28 | 2008-09-03 | 富士通株式会社 | フラッシュメモリを有する電子機器 |
WO2001022232A1 (fr) * | 1999-09-17 | 2001-03-29 | Hitachi, Ltd. | Memoire dans laquelle le nombre de corrections d'erreurs est enregistre |
JP3770171B2 (ja) * | 2002-02-01 | 2006-04-26 | ソニー株式会社 | メモリ装置およびそれを用いたメモリシステム |
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JP4256175B2 (ja) * | 2003-02-04 | 2009-04-22 | 株式会社東芝 | 不揮発性半導体メモリ |
US6930909B2 (en) * | 2003-06-25 | 2005-08-16 | Micron Technology, Inc. | Memory device and methods of controlling resistance variation and resistance profile drift |
US20050177679A1 (en) * | 2004-02-06 | 2005-08-11 | Alva Mauricio H. | Semiconductor memory device |
JP2006134398A (ja) * | 2004-11-04 | 2006-05-25 | Sony Corp | 記憶装置及び半導体装置 |
JP4282612B2 (ja) * | 2005-01-19 | 2009-06-24 | エルピーダメモリ株式会社 | メモリ装置及びそのリフレッシュ方法 |
US7453715B2 (en) * | 2005-03-30 | 2008-11-18 | Ovonyx, Inc. | Reading a phase change memory |
JP4537909B2 (ja) * | 2005-08-08 | 2010-09-08 | 株式会社東芝 | 情報記録装置 |
-
2007
- 2007-10-17 JP JP2007269772A patent/JP5049733B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-17 US US12/672,083 patent/US20100211725A1/en not_active Abandoned
- 2008-10-17 CN CN201310603463.2A patent/CN103594115A/zh active Pending
- 2008-10-17 CN CN2008801116987A patent/CN101828234B/zh active Active
- 2008-10-17 KR KR1020107003299A patent/KR20100044213A/ko not_active Application Discontinuation
- 2008-10-17 EP EP08840090A patent/EP2198428A4/en not_active Withdrawn
- 2008-10-17 WO PCT/JP2008/069287 patent/WO2009051276A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2009051276A1 (en) | 2009-04-23 |
CN101828234B (zh) | 2013-12-25 |
JP2009099200A (ja) | 2009-05-07 |
CN103594115A (zh) | 2014-02-19 |
US20100211725A1 (en) | 2010-08-19 |
EP2198428A4 (en) | 2010-11-10 |
EP2198428A1 (en) | 2010-06-23 |
CN101828234A (zh) | 2010-09-08 |
KR20100044213A (ko) | 2010-04-29 |
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