JP5046506B2 - 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体 - Google Patents

基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体 Download PDF

Info

Publication number
JP5046506B2
JP5046506B2 JP2005303940A JP2005303940A JP5046506B2 JP 5046506 B2 JP5046506 B2 JP 5046506B2 JP 2005303940 A JP2005303940 A JP 2005303940A JP 2005303940 A JP2005303940 A JP 2005303940A JP 5046506 B2 JP5046506 B2 JP 5046506B2
Authority
JP
Japan
Prior art keywords
film
substrate
gas
silicon
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005303940A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007115797A (ja
JP2007115797A5 (enExample
Inventor
國弘 多田
健索 成嶋
哲 若林
晋 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2005303940A priority Critical patent/JP5046506B2/ja
Priority to PCT/JP2006/318333 priority patent/WO2007046204A1/ja
Priority to TW095138422A priority patent/TWI443719B/zh
Publication of JP2007115797A publication Critical patent/JP2007115797A/ja
Publication of JP2007115797A5 publication Critical patent/JP2007115797A5/ja
Application granted granted Critical
Publication of JP5046506B2 publication Critical patent/JP5046506B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10P72/0461—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54—Apparatus specially adapted for continuous coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H10D64/0112—
    • H10P14/43—
    • H10P14/432—
    • H10P70/234—
    • H10P72/0468—
    • H10P72/3304—

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2005303940A 2005-10-19 2005-10-19 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体 Expired - Fee Related JP5046506B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005303940A JP5046506B2 (ja) 2005-10-19 2005-10-19 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体
PCT/JP2006/318333 WO2007046204A1 (ja) 2005-10-19 2006-09-15 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体
TW095138422A TWI443719B (zh) 2005-10-19 2006-10-18 A substrate processing method, a program and a recording medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005303940A JP5046506B2 (ja) 2005-10-19 2005-10-19 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体

Publications (3)

Publication Number Publication Date
JP2007115797A JP2007115797A (ja) 2007-05-10
JP2007115797A5 JP2007115797A5 (enExample) 2008-11-20
JP5046506B2 true JP5046506B2 (ja) 2012-10-10

Family

ID=37962303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005303940A Expired - Fee Related JP5046506B2 (ja) 2005-10-19 2005-10-19 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体

Country Status (3)

Country Link
JP (1) JP5046506B2 (enExample)
TW (1) TWI443719B (enExample)
WO (1) WO2007046204A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4703364B2 (ja) 2005-10-24 2011-06-15 株式会社東芝 半導体装置及びその製造方法
TW200908129A (en) * 2007-06-22 2009-02-16 Ulvac Inc Method for protecting semiconductor wafer and process for producing semiconductor device
JP2009010043A (ja) * 2007-06-26 2009-01-15 Tokyo Electron Ltd 基板処理方法，基板処理装置，記録媒体
JP5171192B2 (ja) * 2007-09-28 2013-03-27 東京エレクトロン株式会社 金属膜成膜方法
JP2009123793A (ja) * 2007-11-13 2009-06-04 Shimadzu Corp クラスタ型真空処理装置
JP5356522B2 (ja) * 2008-07-31 2013-12-04 東京エレクトロン株式会社 化学処理及び熱処理用高スループット処理システム及びその動作方法
JP2011066060A (ja) * 2009-09-15 2011-03-31 Tokyo Electron Ltd 金属シリサイド膜の形成方法
JP2011100962A (ja) * 2009-10-09 2011-05-19 Tokyo Electron Ltd 成膜方法及びプラズマ処理装置
KR20110093476A (ko) * 2010-02-12 2011-08-18 삼성엘이디 주식회사 기상 증착 시스템, 발광소자 제조방법 및 발광소자
JP5933375B2 (ja) * 2011-09-14 2016-06-08 株式会社日立国際電気 クリーニング方法、半導体装置の製造方法、基板処理装置及びプログラム
JP6121348B2 (ja) * 2014-02-28 2017-04-26 東京エレクトロン株式会社 めっきの前処理方法、記憶媒体およびめっき処理システム
US10217819B2 (en) * 2015-05-20 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor device including metal-2 dimensional material-semiconductor contact
JP5947435B1 (ja) * 2015-08-27 2016-07-06 株式会社日立国際電気 基板処理装置、半導体装置の製造方法、プログラムおよび記録媒体
JP6600588B2 (ja) * 2016-03-17 2019-10-30 東京エレクトロン株式会社 基板搬送機構の洗浄方法及び基板処理システム
JP6439774B2 (ja) * 2016-11-21 2018-12-19 トヨタ自動車株式会社 半導体装置の製造方法
JP2020038929A (ja) * 2018-09-05 2020-03-12 東京エレクトロン株式会社 エッチング方法及びエッチング装置
JP7362258B2 (ja) 2019-02-08 2023-10-17 東京エレクトロン株式会社 基板処理方法及び成膜システム
JP7296806B2 (ja) * 2019-07-16 2023-06-23 東京エレクトロン株式会社 ＲｕＳｉ膜の形成方法及び基板処理システム
KR102516340B1 (ko) * 2020-09-08 2023-03-31 주식회사 유진테크 기판 처리 장치 및 기판 처리 장치의 운용 방법
JP7608980B2 (ja) * 2021-06-22 2025-01-07 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP2025062309A (ja) * 2023-10-02 2025-04-14 東京エレクトロン株式会社 成膜方法及び半導体製造装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04296021A (ja) * 1991-03-26 1992-10-20 Mitsubishi Electric Corp 半導体基板の表面処理方法
JP3086719B2 (ja) * 1991-06-27 2000-09-11 株式会社東芝 表面処理方法
JP3487080B2 (ja) * 1996-06-18 2004-01-13 ソニー株式会社 半導体装置およびその製造方法
JP3201318B2 (ja) * 1997-11-05 2001-08-20 日本電気株式会社 半導体装置の製造方法
JP2002016018A (ja) * 2000-06-30 2002-01-18 Sumitomo Heavy Ind Ltd 基板処理装置及び方法
JP4039385B2 (ja) * 2003-04-22 2008-01-30 東京エレクトロン株式会社 ケミカル酸化膜の除去方法
JP4833512B2 (ja) * 2003-06-24 2011-12-07 東京エレクトロン株式会社 被処理体処理装置、被処理体処理方法及び被処理体搬送方法
US20050230350A1 (en) * 2004-02-26 2005-10-20 Applied Materials, Inc. In-situ dry clean chamber for front end of line fabrication
JP4651955B2 (ja) * 2004-03-03 2011-03-16 東京エレクトロン株式会社 成膜方法

Also Published As

Publication number Publication date
TWI443719B (zh) 2014-07-01
WO2007046204A1 (ja) 2007-04-26
JP2007115797A (ja) 2007-05-10
TW200733206A (en) 2007-09-01

Similar Documents

Publication Publication Date Title
JP5046506B2 (ja) 基板処理装置，基板処理方法，プログラム，プログラムを記録した記録媒体
CN101346802B (zh) 成膜方法和基板处理装置
CN101325174B (zh) Ti膜及TiN膜的成膜方法以及接触结构
US8951913B2 (en) Method for removing native oxide and associated residue from a substrate
CN102365715A (zh) 金属硅化物膜的形成方法
KR101678266B1 (ko) 반도체 장치의 제조 방법 및 제조 장치
CN101606228B (zh) 成膜方法
CN101397653B (zh) 金属膜成膜方法
JP5526189B2 (ja) Ｃｕ膜の形成方法
KR101941766B1 (ko) 기판 처리 방법 및 기억 매체
JP5004432B2 (ja) 金属シリサイド膜を形成する方法、前処理方法、成膜システム、制御プログラムおよびコンピュータ記憶媒体
KR101393898B1 (ko) 니켈막의 성막 방법
WO2024070685A1 (ja) 成膜方法、成膜装置、および成膜システム
JP2008300436A (ja) バリヤ層の形成方法及び処理システム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081003

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081003

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120425

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120629

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120717

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120717

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150727

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees