JP5031985B2 - 多数のボディコンタクト領域を形成できる金属酸化膜半導体電界効果トランジスタデバイス - Google Patents
多数のボディコンタクト領域を形成できる金属酸化膜半導体電界効果トランジスタデバイス Download PDFInfo
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- JP5031985B2 JP5031985B2 JP2004510005A JP2004510005A JP5031985B2 JP 5031985 B2 JP5031985 B2 JP 5031985B2 JP 2004510005 A JP2004510005 A JP 2004510005A JP 2004510005 A JP2004510005 A JP 2004510005A JP 5031985 B2 JP5031985 B2 JP 5031985B2
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- 239000004065 semiconductor Substances 0.000 title claims description 51
- 230000005669 field effect Effects 0.000 title claims description 23
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 23
- 150000004706 metal oxides Chemical class 0.000 title claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 210000000746 body region Anatomy 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- BZCGWAXQDLXLQM-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O.ClP(Cl)(Cl)=O BZCGWAXQDLXLQM-UHFFFAOYSA-N 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (17)
- 上面を有する第1の伝導型の半導体領域と、
上記半導体領域の上部内に、上記上面に隣接して形成された第2の伝導型の複数のソース領域と、
上記半導体領域の上部内に、上記上面に隣接して形成された上記第2の伝導型の複数のドレイン領域と、
上記半導体領域の上部内に、上記上面に隣接して形成され、上記半導体領域よりも高い正味のドーピング濃度を有する上記第1の伝導型の複数のボディコンタクト領域と、
上記半導体領域の上記上面上に形成され、
(a)上記複数のソース領域、上記複数のドレイン領域及び上記複数のボディコンタクト領域のための開口を有する連続した領域からなるゲート電極領域と、
(b)上記ゲート電極領域と上記半導体領域との間に配置されたゲート誘電体層とを含むゲート領域とを備え、
上記上面側から見ると、上記ソース領域及び上記ドレイン領域は、直交する行と列に配列され、上記ボディコンタクト領域の少なくとも一部は、上記ソース領域及び上記ドレイン領域のうちの4つの領域と境界を形成しており、
上記複数のソース領域又は上記複数のドレイン領域に取り囲まれた上記ボディコンタクト領域は、上記ゲート電極領域によって完全に取り囲まれており、
上記上面側から見ると、上記ソース領域及び上記ドレイン領域は、八角形の形状を有し、
上記上面側から見ると、上記ボディコンタクト領域は、正方形又は菱形の形状を有し、
上記ボディコンタクト領域の一部は、2つのソース領域と2つのドレイン領域とに隣接し、
上記ソース領域及び上記ドレイン領域は、上記直交する行及び列内において交互に配置されていることを特徴とする金属酸化膜半導体電界効果トランジスタ。 - 上記第1の伝導型は、p型であり、上記第2の伝導型は、n型であることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記半導体領域は、シリコン半導体領域であることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記ゲート電極領域は、ドープトポリシリコン電極領域であることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記ゲート誘電体は、二酸化シリコンであることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記八角形は、正八角形であることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記八角形は、2つの面対称性を有する細長い八角形であることを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、4つの上記ボディコンタクト領域に隣接することを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、2つの上記ボディコンタクト領域に隣接することを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、1つの上記ボディコンタクト領域に隣接することを特徴とする請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- 多層配線構造をその上部に備える請求項1記載の金属酸化膜半導体電界効果トランジスタ。
- (a)ボディ領域と、(b)複数のボディコンタクト領域と、(c)複数のソース領域と、(d)複数のドレイン領域と、(e)上記複数のソース領域、上記複数のドレイン領域及び上記複数のボディコンタクト領域のための開口を有する連続した領域からなるゲート領域とを備え、
上面側から見ると、上記ソース領域及び上記ドレイン領域は、直交する行と列に配列され、上記ボディコンタクト領域の少なくとも一部は、上記ソース領域及びドレイン領域のうちの4つの領域と境界を形成しており、
上記複数のソース領域又は上記複数のドレイン領域に囲まれた上記ボディコンタクト領域は、上記ゲート電極領域によって完全に取り囲まれ、
上記上面側から見ると、上記ソース領域と上記ドレイン領域は、八角形の形状を有し、
上記上面側から見ると、上記ボディコンタクト領域は、正方形又は菱形の形状を有し、
上記ソース領域及びドレイン領域は、上記直交する行及び列内において交互に配置され、
上記ボディコンタクト領域の一部は、2つのソース領域と2つのドレイン領域とに隣接することを特徴とする金属酸化膜半導体電界効果トランジスタ。 - 上記八角形は、正八角形であることを特徴とする請求項12記載の金属酸化膜半導体電界効果トランジスタ。
- 上記八角形は、2つの面対称性を有する細長い八角形であることを特徴とする請求項12記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、4つの上記ボディコンタクト領域に隣接することを特徴とする請求項12記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、2つの上記ボディコンタクト領域に隣接することを特徴とする請求項12記載の金属酸化膜半導体電界効果トランジスタ。
- 上記各ソース領域は、1つの上記ボディコンタクト領域に隣接することを特徴とする請求項12記載の金属酸化膜半導体電界効果トランジスタ。
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Application Number | Priority Date | Filing Date | Title |
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US10/142,674 | 2002-05-10 | ||
US10/142,674 US6724044B2 (en) | 2002-05-10 | 2002-05-10 | MOSFET device having geometry that permits frequent body contact |
PCT/US2003/014623 WO2003103016A2 (en) | 2002-05-10 | 2003-05-09 | Mosfet device having geometry that permits frequent body contact |
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JP2005530337A JP2005530337A (ja) | 2005-10-06 |
JP5031985B2 true JP5031985B2 (ja) | 2012-09-26 |
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JP2004510005A Expired - Fee Related JP5031985B2 (ja) | 2002-05-10 | 2003-05-09 | 多数のボディコンタクト領域を形成できる金属酸化膜半導体電界効果トランジスタデバイス |
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US (2) | US6724044B2 (ja) |
EP (1) | EP1540737A4 (ja) |
JP (1) | JP5031985B2 (ja) |
CN (1) | CN100539185C (ja) |
AU (1) | AU2003265236A1 (ja) |
TW (1) | TWI282623B (ja) |
WO (1) | WO2003103016A2 (ja) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6936898B2 (en) * | 2002-12-31 | 2005-08-30 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
US7323367B1 (en) * | 2002-12-31 | 2008-01-29 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
US7174528B1 (en) | 2003-10-10 | 2007-02-06 | Transmeta Corporation | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure |
US7851872B2 (en) * | 2003-10-22 | 2010-12-14 | Marvell World Trade Ltd. | Efficient transistor structure |
US7960833B2 (en) * | 2003-10-22 | 2011-06-14 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
US7645673B1 (en) | 2004-02-03 | 2010-01-12 | Michael Pelham | Method for generating a deep N-well pattern for an integrated circuit design |
US7388260B1 (en) | 2004-03-31 | 2008-06-17 | Transmeta Corporation | Structure for spanning gap in body-bias voltage routing structure |
US20050280053A1 (en) * | 2004-06-22 | 2005-12-22 | Hayes Monty B | Semiconductor device with diagonal gate signal distribution runner |
JP2006261437A (ja) * | 2005-03-17 | 2006-09-28 | Mitsumi Electric Co Ltd | 半導体装置 |
US7305647B1 (en) | 2005-07-28 | 2007-12-04 | Transmeta Corporation | Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage |
TWI429078B (zh) * | 2006-05-08 | 2014-03-01 | Marvell World Trade Ltd | 有效率電晶體結構 |
JP2008078469A (ja) * | 2006-09-22 | 2008-04-03 | Texas Instr Japan Ltd | 電界効果トランジスタ |
CN101657901B (zh) * | 2006-12-28 | 2012-07-04 | 马维尔国际贸易有限公司 | 具有低导通电阻的mos器件的几何图形 |
CN101652858A (zh) * | 2007-03-15 | 2010-02-17 | 马维尔国际贸易有限公司 | 集成电路和集成电路的互连结构 |
WO2010013195A1 (en) * | 2008-07-28 | 2010-02-04 | Nxp B.V. | Integrated circuit and method for manufacturing an integrated circuit |
JP4577428B2 (ja) * | 2008-08-11 | 2010-11-10 | ソニー株式会社 | 表示装置、表示方法及びプログラム |
CA2769940C (en) * | 2009-08-04 | 2016-04-26 | Gan Systems Inc. | Island matrixed gallium nitride microwave and power switching transistors |
US9029866B2 (en) | 2009-08-04 | 2015-05-12 | Gan Systems Inc. | Gallium nitride power devices using island topography |
US9818857B2 (en) | 2009-08-04 | 2017-11-14 | Gan Systems Inc. | Fault tolerant design for large area nitride semiconductor devices |
JP2011040675A (ja) * | 2009-08-18 | 2011-02-24 | Sumitomo Electric Ind Ltd | 半導体装置 |
DE102010001788A1 (de) * | 2010-02-10 | 2011-08-11 | Forschungsverbund Berlin e.V., 12489 | Skalierbarer Aufbau für laterale Halbleiterbauelemente mit hoher Stromtragfähigkeit |
CN102623496B (zh) * | 2011-01-27 | 2014-11-05 | 无锡华润上华半导体有限公司 | 矩阵型mos场效应晶体管 |
US8941175B2 (en) * | 2013-06-17 | 2015-01-27 | United Microelectronics Corp. | Power array with staggered arrangement for improving on-resistance and safe operating area |
KR20150092828A (ko) * | 2014-02-06 | 2015-08-17 | 정덕영 | 배터리의 충방전 제어회로를 위한 4-단자 fet |
US10345967B2 (en) * | 2014-09-17 | 2019-07-09 | Red Hat, Inc. | User interface for a device |
CN104881181B (zh) * | 2015-05-27 | 2019-07-26 | 联想(北京)有限公司 | 显示方法及电子设备 |
US10847445B2 (en) * | 2016-03-31 | 2020-11-24 | Skyworks Solutions, Inc. | Non-symmetric body contacts for field-effect transistors |
US20200013901A1 (en) * | 2018-07-03 | 2020-01-09 | Stmicroelectronics Sa | Substrate contact for a transistor, intended in particular for a matrix-array arrangement |
CN110299356A (zh) * | 2019-07-26 | 2019-10-01 | 宁波芯浪电子科技有限公司 | 一种用于mos管的静电保护方法 |
CN112447836A (zh) * | 2019-08-30 | 2021-03-05 | 广东致能科技有限公司 | 一种具有高耐压能力的高电子迁移率晶体管 |
CN110534512B (zh) * | 2019-09-07 | 2023-02-07 | 电子科技大学 | 一种抗闩锁版图结构 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62104173A (ja) * | 1985-10-31 | 1987-05-14 | Fujitsu Ltd | 半導体装置 |
US5079605A (en) * | 1988-07-29 | 1992-01-07 | Texas Instruments Incorporated | Silicon-on-insulator transistor with selectable body node to source node connection |
JPH03206667A (ja) * | 1990-01-09 | 1991-09-10 | Seiko Instr Inc | Mosトランジスタ |
JP3156300B2 (ja) * | 1991-10-07 | 2001-04-16 | 株式会社デンソー | 縦型半導体装置 |
US5355008A (en) | 1993-11-19 | 1994-10-11 | Micrel, Inc. | Diamond shaped gate mesh for cellular MOS transistor array |
JP3369388B2 (ja) * | 1996-01-30 | 2003-01-20 | 株式会社東芝 | 半導体装置 |
KR100225944B1 (ko) * | 1996-06-24 | 1999-10-15 | 김영환 | 가변 드레인 전류형 트랜지스터를 갖는 반도체 장치 |
US6140687A (en) * | 1996-11-28 | 2000-10-31 | Matsushita Electric Industrial Co., Ltd. | High frequency ring gate MOSFET |
JP3276325B2 (ja) * | 1996-11-28 | 2002-04-22 | 松下電器産業株式会社 | 半導体装置 |
US5972804A (en) * | 1997-08-05 | 1999-10-26 | Motorola, Inc. | Process for forming a semiconductor device |
JP3855386B2 (ja) * | 1997-08-27 | 2006-12-06 | 日産自動車株式会社 | 半導体装置 |
US6140167A (en) * | 1998-08-18 | 2000-10-31 | Advanced Micro Devices, Inc. | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation |
TW447129B (en) * | 2000-06-30 | 2001-07-21 | United Microelectronics Corp | Array type SOI transistor layout |
-
2002
- 2002-05-10 US US10/142,674 patent/US6724044B2/en not_active Expired - Fee Related
-
2003
- 2003-05-07 TW TW092112458A patent/TWI282623B/zh active
- 2003-05-09 CN CNB03810606XA patent/CN100539185C/zh not_active Expired - Fee Related
- 2003-05-09 WO PCT/US2003/014623 patent/WO2003103016A2/en active Application Filing
- 2003-05-09 JP JP2004510005A patent/JP5031985B2/ja not_active Expired - Fee Related
- 2003-05-09 EP EP03756172A patent/EP1540737A4/en not_active Withdrawn
- 2003-05-09 AU AU2003265236A patent/AU2003265236A1/en not_active Abandoned
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2004
- 2004-04-19 US US10/827,676 patent/US20050001272A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20050001272A1 (en) | 2005-01-06 |
AU2003265236A8 (en) | 2003-12-19 |
US20030209759A1 (en) | 2003-11-13 |
WO2003103016A3 (en) | 2005-04-21 |
CN1777997A (zh) | 2006-05-24 |
EP1540737A4 (en) | 2010-11-24 |
TWI282623B (en) | 2007-06-11 |
WO2003103016A2 (en) | 2003-12-11 |
EP1540737A2 (en) | 2005-06-15 |
CN100539185C (zh) | 2009-09-09 |
US6724044B2 (en) | 2004-04-20 |
AU2003265236A1 (en) | 2003-12-19 |
JP2005530337A (ja) | 2005-10-06 |
TW200308092A (en) | 2003-12-16 |
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