JP5000433B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5000433B2 JP5000433B2 JP2007226776A JP2007226776A JP5000433B2 JP 5000433 B2 JP5000433 B2 JP 5000433B2 JP 2007226776 A JP2007226776 A JP 2007226776A JP 2007226776 A JP2007226776 A JP 2007226776A JP 5000433 B2 JP5000433 B2 JP 5000433B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signals
- active
- sense amplifier
- precharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/065—Sense amplifier drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4065—Low level details of refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2006-0099545 | 2006-10-12 | ||
| KR1020060099545A KR100821580B1 (ko) | 2006-10-12 | 2006-10-12 | 반도체 메모리 장치 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008097806A JP2008097806A (ja) | 2008-04-24 |
| JP2008097806A5 JP2008097806A5 (enExample) | 2010-09-30 |
| JP5000433B2 true JP5000433B2 (ja) | 2012-08-15 |
Family
ID=39302948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007226776A Active JP5000433B2 (ja) | 2006-10-12 | 2007-08-31 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7583548B2 (enExample) |
| JP (1) | JP5000433B2 (enExample) |
| KR (1) | KR100821580B1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9356397B2 (en) | 2012-01-19 | 2016-05-31 | Asustek Computer Inc. | Connector and electronic system using the same |
| US11361815B1 (en) | 2020-12-24 | 2022-06-14 | Winbond Electronics Corp. | Method and memory device including plurality of memory banks and having shared delay circuit |
| TWI761124B (zh) * | 2021-03-12 | 2022-04-11 | 華邦電子股份有限公司 | 具有共用延遲電路的方法和記憶體裝置 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3244340B2 (ja) * | 1993-05-24 | 2002-01-07 | 三菱電機株式会社 | 同期型半導体記憶装置 |
| KR960009953B1 (ko) * | 1994-01-27 | 1996-07-25 | 삼성전자 주식회사 | 반도체 메모리 장치의 센스앰프 제어회로 |
| JP3696633B2 (ja) * | 1994-07-27 | 2005-09-21 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| KR100242720B1 (ko) * | 1996-12-30 | 2000-02-01 | 윤종용 | 반도체 메모리 장치의 칼럼선택 제어회로 |
| KR100271626B1 (ko) | 1997-05-31 | 2000-12-01 | 김영환 | 비트라인 센스앰프의 오버드라이빙방법 |
| KR100273274B1 (ko) | 1998-01-21 | 2001-01-15 | 김영환 | 오버 드라이빙 제어회로 |
| KR100271644B1 (ko) | 1998-02-06 | 2000-12-01 | 김영환 | 센스앰프 오버드라이빙 전압제어 회로 |
| JP3544863B2 (ja) | 1998-06-29 | 2004-07-21 | 富士通株式会社 | 半導体メモリ及びこれを備えた半導体装置 |
| JP2001167574A (ja) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6347058B1 (en) | 2000-05-19 | 2002-02-12 | International Business Machines Corporation | Sense amplifier with overdrive and regulated bitline voltage |
| KR20020042030A (ko) * | 2000-11-29 | 2002-06-05 | 윤종용 | 리프레쉬 수행시간이 감소될 수 있는 다중 뱅크를구비하는 반도체 메모리 장치 및 리프레쉬 방법 |
| KR100378685B1 (ko) | 2000-12-29 | 2003-04-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그의 센스 앰프 제어 회로 |
| KR100427028B1 (ko) * | 2001-12-18 | 2004-04-14 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
| KR100495918B1 (ko) | 2002-12-16 | 2005-06-17 | 주식회사 하이닉스반도체 | 뱅크의 액티브 동작을 달리하는 반도체 기억 장치 및반도체 기억 장치에서의 뱅크 액티브 제어 방법 |
| KR100587639B1 (ko) | 2003-05-30 | 2006-06-08 | 주식회사 하이닉스반도체 | 계층화된 출력배선의 감지증폭기 드라이버를 구비한반도체 메모리 소자 |
| KR100546333B1 (ko) * | 2003-06-25 | 2006-01-26 | 삼성전자주식회사 | 감지 증폭기 드라이버 및 이를 구비하는 반도체 장치 |
| KR20050101872A (ko) * | 2004-04-20 | 2005-10-25 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| US7127368B2 (en) | 2004-11-19 | 2006-10-24 | Stmicroelectronics Asia Pacific Pte. Ltd. | On-chip temperature sensor for low voltage operation |
| KR100656470B1 (ko) * | 2006-02-07 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 드라이버 제어장치 및 방법 |
-
2006
- 2006-10-12 KR KR1020060099545A patent/KR100821580B1/ko active Active
-
2007
- 2007-07-09 US US11/822,655 patent/US7583548B2/en active Active
- 2007-08-31 JP JP2007226776A patent/JP5000433B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20080089149A1 (en) | 2008-04-17 |
| US7583548B2 (en) | 2009-09-01 |
| KR100821580B1 (ko) | 2008-04-15 |
| JP2008097806A (ja) | 2008-04-24 |
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