JP4984552B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4984552B2
JP4984552B2 JP2006021029A JP2006021029A JP4984552B2 JP 4984552 B2 JP4984552 B2 JP 4984552B2 JP 2006021029 A JP2006021029 A JP 2006021029A JP 2006021029 A JP2006021029 A JP 2006021029A JP 4984552 B2 JP4984552 B2 JP 4984552B2
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chip
adhesive layer
wiring
semiconductor device
wire
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JP2006021029A
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JP2007201368A (ja
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紘宇 下川
直生 和泉
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2006021029A priority Critical patent/JP4984552B2/ja
Priority to US11/699,568 priority patent/US20070178623A1/en
Publication of JP2007201368A publication Critical patent/JP2007201368A/ja
Priority to US12/648,276 priority patent/US20100167468A1/en
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Publication of JP4984552B2 publication Critical patent/JP4984552B2/ja
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Description

本発明は、配線基板上に接着層を介してチップを接着した後、超音波振動を印加しながらチップ上のパッドにワイヤをボンディングする半導体装置の製造方法に関するものである。
リードフレーム又は配線基板上にチップを接着する際に、フィルム状の接着層が用いられている（例えば、特許文献１参照）。ここで、配線基板の表面には５μｍ〜２０μｍの凹凸があるため、接着層と配線基板との間に隙間ができる。これに対し、接着層が柔らかい場合、樹脂封止の際の圧力で当該隙間の空気は抜けるため何ら問題は無い。一方、接着層が硬い場合、当該隙間の空気は抜け難いためボイドとして残り、パッケージの実装の際の熱等でチップが割れる原因となる。このため、従来は、接着層としてワイヤボンディング工程におけるプロセス温度での弾性率が１０ＭＰａ以下のものを用いていた。
また、配線基板上に接着層を介してチップを接着した後、チップ上のパッドにワイヤをボンディングする。この際に、超音波を印加することにより、パッド表面の酸化膜を破壊して、パッドとワイヤの接合強度を向上させていた。
特開２００３−１１９４４０号公報
近年、４ビット〜１６ビットのマイコン等において、チップサイズが３ｍｍ角以下のチップが用いられるようになってきた。このような小さなチップと配線基板との接着面積は小さいため、チップと配線基板の接合強度も小さい。これにより、ワイヤボンディング工程において、超音波振動に併せてチップが揺れ動くため、パッド表面の酸化膜を十分に破壊することができず、パッドとワイヤの接合強度が低下するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は、チップ上のパッドとワイヤの接合強度を向上させることができる半導体装置の製造方法を得るものである。
本発明に係る半導体装置の製造方法は、配線基板上に接着層を介してチップを接着する接着工程と、前記接着工程の後に、超音波振動を印加しながら前記チップ上のパッドにワイヤをボンディングするワイヤボンディング工程とを有し、前記接着層は、前記チップの裏面と同一平面形状を有するフィルム状の接着層であり、かつ、前記ワイヤボンディング工程におけるプロセス温度での弾性率が１００ＭＰａ以上であり、前記配線基板は、その表面に形成されたＣｕ配線パターンと前記Ｃｕ配線パターンを覆うように形成されたソルダレジスト膜を有し、前記チップは、前記Ｃｕ配線パターン上の前記ソルダレジスト膜に接着され、前記チップの接着領域において、前記Ｃｕ配線パターンは、９０％以上の占有率であり、前記Ｃｕ配線パターンは、複数の信号配線パターンと、前記複数の信号配線パターンを平面的に囲むように隣接して形成され、かつ、前記複数の信号配線パターンよりも幅の広い電源/ＧＮＤパターンを有し、前記電源/ＧＮＤパターンは、前記チップの接着領域の中心から外側の領域に連続するスリットを有する。本発明のその他の特徴は以下に明らかにする。
本発明により、ワイヤボンディング工程において超音波振動に併せてチップが揺れ動くのを抑制し、チップ上のパッドとワイヤの接合強度を向上させることができる。
以下、本発明の実施の形態に係る半導体装置の製造方法について図面を用いて説明する。
まず、図１に示すような配線基板１を用意する。この配線基板１には、図２に示す構造が複数個配列されている。また、図３は配線基板の断面図である。図示のように、配線基板１には、複数のＣｕ配線２が設けられ、表面がソルダーレジスト３で覆われている。
図４は配線基板の要部を拡大した断面図である。Ｃｕ配線２の配線基板１上での厚みは１８μｍであり、Ｃｕ配線２とソルダーレジスト３の合計の厚みは３３μｍである。そして、Ｃｕ配線２同士の間でソルダーレジスト３が窪むため、ソルダーレジスト３の表面には５〜２０μｍの凹凸が形成される。
次に、図５及び図６に示すように、配線基板１上に接着層４を介して３ｍｍ角のチップ５を接着する。この際、接着層４として、後述のワイヤボンディング工程におけるプロセス温度での弾性率が１００ＭＰａ以上のものを用いる。このように弾性率の高い接着層４を用いるため、図７に示すように、ソルダーレジスト３と接着層４の間に微小な隙間が形成される。接着層４の厚さは、半導体装置の薄型化のために、２５μｍ以下となっている。
次に、図８及び図９に示すように、チップ５上に接着層６を介して２ｍｍ角のスペーサチップ７を搭載する。なお、接着層６は、接着層４と同様の物質からなる。
次に、図１０に示すように、配線基板１をステージ８の上に載せる。そして、キャピラリ９から排出した金ワイヤ１０の先端の金ボールを、キャピラリ９により超音波振動を印加しながら、チップ５上のパッド１１に押圧してボンディングする。この際、キャピラリ９による荷重は２０〜８０ｇ、超音波振動の振幅は１μｍ程度、振動数は６０〜１２０ｋＨｚとする。そして、図１１及び図１２に示すように、金ワイヤ１０の他端は配線基板１の配線２にボンディングする。
上記のように、接着層４としてワイヤボンディング工程におけるプロセス温度での弾性率が１００ＭＰａ以上のものを用いることにより、ワイヤボンディング工程において超音波振動に併せてチップ５が揺れ動くのを抑制し、チップ５上のパッド１１と金ワイヤ１０の接合強度を向上させることができる。
この効果は特にチップ５としてチップサイズが３ｍｍ角以下のものを用いた場合に顕著となる。そして、このような小さなチップであれば、弾性率が高い接着層４を用いても、接着層４と配線基板１との間から空気が抜け易い。また、チップ５として、短辺が３ｍｍ以下のものや、面積が９ｍｍ２以下のものを用いた場合も同様である。
また、チップ５上のパッド１１と金ワイヤ１０の接合強度を確保するために、ワイヤボンディング工程におけるプロセス温度は１００℃以上にするのが好ましく、１５０℃以上にするのが特に好ましい。具体的には、配線基板１を載せたステージ８の温度を１６０℃に設定して、チップ５側へ熱を供給する。
次に、図１３及び図１４に示すように、スペーサチップ７上に接着層１２を介して３ｍｍ角のチップ１３を搭載する。なお、接着層１２は、接着層４と同様の物質からなる。そして、図１５及び図１６に示すように、上記と同様に、チップ１３上のパッド１４と配線基板１上のＣｕ配線２にワイヤ１５をボンディングする。
次に、図１７に示すように、配線基板１上をトランスファーモールド法により樹脂１６で樹脂封止する。この際、樹脂注入時の圧力を８ＭＰａ以上にする。この樹脂注入時の圧力により、図１８に示すように、接着層４と配線基板１との間から空気を追い出すことができる。樹脂１６は、熱硬化性のエポキシ樹脂などにより形成され、トランスファーモールド時の工程温度は例えば１８０℃である。接着層４としては、弾性率が高すぎると、トランスファーモールド時に樹脂から圧力を受けた場合に、配線基板１表面の凹凸に馴染む形への変形が十分に進まないため、ある程度以下の弾性率であることが好ましい。具体的には、トランスファーモールドの工程温度における接着層４の弾性率が１ＧＰａ以下であることが好ましい。特に、半導体装置の薄型化のために、接着層４の厚さが２５μｍ以下と薄型化されている場合には、適当な弾性率を有する接着層４の選択は重要となる。以上の工程により、本実施の形態に係る半導体装置が製造される。
ここで、接着層４としてペースト状のものを用いると、チップ５と配線基板１との間から接着層４がはみ出し易いという問題がある。特に、チップ５の端と配線基板１上のＣｕ配線２との間隔を０．５ｍｍ以下とする場合、はみ出した接着層４が配線基板１上のＣｕ配線２に達して不良を生じる原因となる。また、チップ５として、チップ厚が１００μｍ以下のものを用いた場合、はみ出した接着層４がチップ５上に這い上がって不良を生じる原因となる。そこで、接着層４としてフィルム状のものを用いるのが好ましい。
そして、フィルム状の接着層４を用いる場合、複数のチップ５が形成されたウェハの裏面に接着層４を貼り付けた後に、チップ５ごとにウェハを切断することで、製造工程を簡略化することができる。また、弾性率を高くするために、接着層４として、シリカフィラーやＢＮフィラー等の無機フィラーが１０ｗｔ％以上、好ましくは５０ｗｔ％以上含有するものを用いる。
また、配線基板１表面の凹部とチップとの隙間に空気が残るとボイドとなる。このボイドによるチップ５の割れを防ぐためには、最終形態でのチップ５下におけるボイドの割合を１割以下にする必要がある。そこで、図１９に示すように、配線基板１としてチップ５を接着する表面領域においてＣｕ配線２がある部分が９０％以上のものを用いる。チップ５を接着する領域の配線としては、フローティング電位のダミー配線パターンや、電源電位もしくは接地電位電極と接続する電源／ＧＮＤ配線パターンの幅を、信号用配線の幅に比べて広く形成する事によってその領域を調整するのが好ましい。また、信号用配線の幅は、これら幅広配線に比べて、細く、ほぼ均一にすることにより、スタブ配線の形成や、インピーダンスの不整合によるノイズ源の形成などを防ぐことができる。チップ下領域の幅広配線パターン形状としては、図１９に示すように、チップ外の領域に連続するスリットが形成されていることが好ましい。チップ外の領域に連続する放射状のスリットが形成されていることにより、チップの下に取り残されたボイドを効果的にチップ外に排出することができる。
また、配線基板１として表面の凹凸の深さが１０μｍ以下、より好ましくは２μｍ以下のものを用いることにより、配線基板１の表面の凹部に接着層４が入り込み易くなるため、チップ５と配線基板１の接合強度を更に向上させることができる。配線基板１表面の凹凸の深さを低くする手段としては、例えば、ソルダーレジストを２層に分けて塗布する方法や、ドライフィルムレジストを使用し、ラミネートローラーによる熱圧着によって形成する方法などが選択可能である。
配線基板全体を示す平面図である。 配線基板を示す平面図である。 配線基板を示す断面図である。 図３に示す配線基板の要部を拡大した断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 図６に示す半導体装置の要部を拡大した断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 ワイヤボンディング工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 図１７に示す半導体装置の要部を拡大した断面図である。 チップを接着する表面領域においてＣｕ配線がある部分が９０％以上の配線基板を示す平面図である。
符号の説明
１ 配線基板
２ Ｃｕ配線（配線）
４ 接着層
５ チップ
１０ 金ワイヤ（ワイヤ）
１１ パッド
１６ 樹脂

Claims (1)

  1. 配線基板上に接着層を介してチップを接着する接着工程と、
    前記接着工程の後に、超音波振動を印加しながら前記チップ上のパッドにワイヤをボンディングするワイヤボンディング工程とを有し、
    前記接着層は、前記チップの裏面と同一平面形状を有するフィルム状の接着層であり、かつ、前記ワイヤボンディング工程におけるプロセス温度での弾性率が１００ＭＰａ以上であり、
    前記配線基板は、その表面に形成されたＣｕ配線パターンと前記Ｃｕ配線パターンを覆うように形成されたソルダレジスト膜を有し、
    前記チップは、前記Ｃｕ配線パターン上の前記ソルダレジスト膜に接着され、前記チップの接着領域において、前記Ｃｕ配線パターンは、９０％以上の占有率であり、
    前記Ｃｕ配線パターンは、複数の信号配線パターンと、前記複数の信号配線パターンを平面的に囲むように隣接して形成され、かつ、前記複数の信号配線パターンよりも幅の広い電源/ＧＮＤパターンを有し、
    前記電源/ＧＮＤパターンは、前記チップの接着領域の中心から外側の領域に連続するスリットを有することを特徴とする半導体装置の製造方法。
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