JP4984552B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4984552B2 JP4984552B2 JP2006021029A JP2006021029A JP4984552B2 JP 4984552 B2 JP4984552 B2 JP 4984552B2 JP 2006021029 A JP2006021029 A JP 2006021029A JP 2006021029 A JP2006021029 A JP 2006021029A JP 4984552 B2 JP4984552 B2 JP 4984552B2
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
2 Cu配線(配線)
4 接着層
5 チップ
10 金ワイヤ(ワイヤ)
11 パッド
16 樹脂
Claims (1)
- 配線基板上に接着層を介してチップを接着する接着工程と、
前記接着工程の後に、超音波振動を印加しながら前記チップ上のパッドにワイヤをボンディングするワイヤボンディング工程とを有し、
前記接着層は、前記チップの裏面と同一平面形状を有するフィルム状の接着層であり、かつ、前記ワイヤボンディング工程におけるプロセス温度での弾性率が100MPa以上であり、
前記配線基板は、その表面に形成されたCu配線パターンと前記Cu配線パターンを覆うように形成されたソルダレジスト膜を有し、
前記チップは、前記Cu配線パターン上の前記ソルダレジスト膜に接着され、前記チップの接着領域において、前記Cu配線パターンは、90%以上の占有率であり、
前記Cu配線パターンは、複数の信号配線パターンと、前記複数の信号配線パターンを平面的に囲むように隣接して形成され、かつ、前記複数の信号配線パターンよりも幅の広い電源/GNDパターンを有し、
前記電源/GNDパターンは、前記チップの接着領域の中心から外側の領域に連続するスリットを有することを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006021029A JP4984552B2 (ja) | 2006-01-30 | 2006-01-30 | 半導体装置の製造方法 |
US11/699,568 US20070178623A1 (en) | 2006-01-30 | 2007-01-30 | Method of manufacturing semiconductor device |
US12/648,276 US20100167468A1 (en) | 2006-01-30 | 2009-12-28 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006021029A JP4984552B2 (ja) | 2006-01-30 | 2006-01-30 | 半導体装置の製造方法 |
Publications (2)
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JP2007201368A JP2007201368A (ja) | 2007-08-09 |
JP4984552B2 true JP4984552B2 (ja) | 2012-07-25 |
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JP2006021029A Expired - Fee Related JP4984552B2 (ja) | 2006-01-30 | 2006-01-30 | 半導体装置の製造方法 |
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US (2) | US20070178623A1 (ja) |
JP (1) | JP4984552B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009206429A (ja) * | 2008-02-29 | 2009-09-10 | Toshiba Corp | 記憶媒体 |
JP5135164B2 (ja) | 2008-10-22 | 2013-01-30 | 株式会社東芝 | ボンディング方法 |
JP5147755B2 (ja) * | 2009-02-20 | 2013-02-20 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP5680330B2 (ja) * | 2010-04-23 | 2015-03-04 | 株式会社東芝 | 半導体装置の製造方法 |
US8767351B1 (en) * | 2013-01-31 | 2014-07-01 | Seagate Technology Llc | Ambient temperature ball bond |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
US6414391B1 (en) * | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
EP0987747A1 (en) * | 1998-09-17 | 2000-03-22 | STMicroelectronics S.r.l. | Process for improving the adhesion between metal and plastic in containment structures for electronic semiconductor devices |
JP2000223613A (ja) * | 1999-01-28 | 2000-08-11 | Citizen Watch Co Ltd | 半導体装置 |
US6329722B1 (en) * | 1999-07-01 | 2001-12-11 | Texas Instruments Incorporated | Bonding pads for integrated circuits having copper interconnect metallization |
JP2001244303A (ja) * | 2000-02-25 | 2001-09-07 | Hitachi Chem Co Ltd | 半導体搭載用基板に用いる接着剤付絶縁基材とその製造方法とそれを用いた半導体搭載用基板並びにその製造方法 |
JP4573412B2 (ja) * | 2000-09-01 | 2010-11-04 | ローム株式会社 | 半導体装置 |
US6768212B2 (en) * | 2002-01-24 | 2004-07-27 | Texas Instruments Incorporated | Semiconductor packages and methods for manufacturing such semiconductor packages |
JP4114567B2 (ja) * | 2003-07-30 | 2008-07-09 | 日立化成工業株式会社 | 半導体装置およびその製造方法 |
US7425759B1 (en) * | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
-
2006
- 2006-01-30 JP JP2006021029A patent/JP4984552B2/ja not_active Expired - Fee Related
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2007
- 2007-01-30 US US11/699,568 patent/US20070178623A1/en not_active Abandoned
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- 2009-12-28 US US12/648,276 patent/US20100167468A1/en not_active Abandoned
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JP2007201368A (ja) | 2007-08-09 |
US20100167468A1 (en) | 2010-07-01 |
US20070178623A1 (en) | 2007-08-02 |
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