JP4984552B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4984552B2
JP4984552B2 JP2006021029A JP2006021029A JP4984552B2 JP 4984552 B2 JP4984552 B2 JP 4984552B2 JP 2006021029 A JP2006021029 A JP 2006021029A JP 2006021029 A JP2006021029 A JP 2006021029A JP 4984552 B2 JP4984552 B2 JP 4984552B2
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Prior art keywords
chip
adhesive layer
wiring
semiconductor device
wire
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JP2006021029A
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JP2007201368A (ja
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紘宇 下川
直生 和泉
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2006021029A priority Critical patent/JP4984552B2/ja
Priority to US11/699,568 priority patent/US20070178623A1/en
Publication of JP2007201368A publication Critical patent/JP2007201368A/ja
Priority to US12/648,276 priority patent/US20100167468A1/en
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Description

本発明は、配線基板上に接着層を介してチップを接着した後、超音波振動を印加しながらチップ上のパッドにワイヤをボンディングする半導体装置の製造方法に関するものである。
リードフレーム又は配線基板上にチップを接着する際に、フィルム状の接着層が用いられている(例えば、特許文献1参照)。ここで、配線基板の表面には5μm〜20μmの凹凸があるため、接着層と配線基板との間に隙間ができる。これに対し、接着層が柔らかい場合、樹脂封止の際の圧力で当該隙間の空気は抜けるため何ら問題は無い。一方、接着層が硬い場合、当該隙間の空気は抜け難いためボイドとして残り、パッケージの実装の際の熱等でチップが割れる原因となる。このため、従来は、接着層としてワイヤボンディング工程におけるプロセス温度での弾性率が10MPa以下のものを用いていた。
また、配線基板上に接着層を介してチップを接着した後、チップ上のパッドにワイヤをボンディングする。この際に、超音波を印加することにより、パッド表面の酸化膜を破壊して、パッドとワイヤの接合強度を向上させていた。
特開2003−119440号公報
近年、4ビット〜16ビットのマイコン等において、チップサイズが3mm角以下のチップが用いられるようになってきた。このような小さなチップと配線基板との接着面積は小さいため、チップと配線基板の接合強度も小さい。これにより、ワイヤボンディング工程において、超音波振動に併せてチップが揺れ動くため、パッド表面の酸化膜を十分に破壊することができず、パッドとワイヤの接合強度が低下するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は、チップ上のパッドとワイヤの接合強度を向上させることができる半導体装置の製造方法を得るものである。
本発明に係る半導体装置の製造方法は、配線基板上に接着層を介してチップを接着する接着工程と、前記接着工程の後に、超音波振動を印加しながら前記チップ上のパッドにワイヤをボンディングするワイヤボンディング工程とを有し、前記接着層は、前記チップの裏面と同一平面形状を有するフィルム状の接着層であり、かつ、前記ワイヤボンディング工程におけるプロセス温度での弾性率が100MPa以上であり、前記配線基板は、その表面に形成されたCu配線パターンと前記Cu配線パターンを覆うように形成されたソルダレジスト膜を有し、前記チップは、前記Cu配線パターン上の前記ソルダレジスト膜に接着され、前記チップの接着領域において、前記Cu配線パターンは、90%以上の占有率であり、前記Cu配線パターンは、複数の信号配線パターンと、前記複数の信号配線パターンを平面的に囲むように隣接して形成され、かつ、前記複数の信号配線パターンよりも幅の広い電源/GNDパターンを有し、前記電源/GNDパターンは、前記チップの接着領域の中心から外側の領域に連続するスリットを有する。本発明のその他の特徴は以下に明らかにする。
本発明により、ワイヤボンディング工程において超音波振動に併せてチップが揺れ動くのを抑制し、チップ上のパッドとワイヤの接合強度を向上させることができる。
以下、本発明の実施の形態に係る半導体装置の製造方法について図面を用いて説明する。
まず、図1に示すような配線基板1を用意する。この配線基板1には、図2に示す構造が複数個配列されている。また、図3は配線基板の断面図である。図示のように、配線基板1には、複数のCu配線2が設けられ、表面がソルダーレジスト3で覆われている。
図4は配線基板の要部を拡大した断面図である。Cu配線2の配線基板1上での厚みは18μmであり、Cu配線2とソルダーレジスト3の合計の厚みは33μmである。そして、Cu配線2同士の間でソルダーレジスト3が窪むため、ソルダーレジスト3の表面には5〜20μmの凹凸が形成される。
次に、図5及び図6に示すように、配線基板1上に接着層4を介して3mm角のチップ5を接着する。この際、接着層4として、後述のワイヤボンディング工程におけるプロセス温度での弾性率が100MPa以上のものを用いる。このように弾性率の高い接着層4を用いるため、図7に示すように、ソルダーレジスト3と接着層4の間に微小な隙間が形成される。接着層4の厚さは、半導体装置の薄型化のために、25μm以下となっている。
次に、図8及び図9に示すように、チップ5上に接着層6を介して2mm角のスペーサチップ7を搭載する。なお、接着層6は、接着層4と同様の物質からなる。
次に、図10に示すように、配線基板1をステージ8の上に載せる。そして、キャピラリ9から排出した金ワイヤ10の先端の金ボールを、キャピラリ9により超音波振動を印加しながら、チップ5上のパッド11に押圧してボンディングする。この際、キャピラリ9による荷重は20〜80g、超音波振動の振幅は1μm程度、振動数は60〜120kHzとする。そして、図11及び図12に示すように、金ワイヤ10の他端は配線基板1の配線2にボンディングする。
上記のように、接着層4としてワイヤボンディング工程におけるプロセス温度での弾性率が100MPa以上のものを用いることにより、ワイヤボンディング工程において超音波振動に併せてチップ5が揺れ動くのを抑制し、チップ5上のパッド11と金ワイヤ10の接合強度を向上させることができる。
この効果は特にチップ5としてチップサイズが3mm角以下のものを用いた場合に顕著となる。そして、このような小さなチップであれば、弾性率が高い接着層4を用いても、接着層4と配線基板1との間から空気が抜け易い。また、チップ5として、短辺が3mm以下のものや、面積が9mm以下のものを用いた場合も同様である。
また、チップ5上のパッド11と金ワイヤ10の接合強度を確保するために、ワイヤボンディング工程におけるプロセス温度は100℃以上にするのが好ましく、150℃以上にするのが特に好ましい。具体的には、配線基板1を載せたステージ8の温度を160℃に設定して、チップ5側へ熱を供給する。
次に、図13及び図14に示すように、スペーサチップ7上に接着層12を介して3mm角のチップ13を搭載する。なお、接着層12は、接着層4と同様の物質からなる。そして、図15及び図16に示すように、上記と同様に、チップ13上のパッド14と配線基板1上のCu配線2にワイヤ15をボンディングする。
次に、図17に示すように、配線基板1上をトランスファーモールド法により樹脂16で樹脂封止する。この際、樹脂注入時の圧力を8MPa以上にする。この樹脂注入時の圧力により、図18に示すように、接着層4と配線基板1との間から空気を追い出すことができる。樹脂16は、熱硬化性のエポキシ樹脂などにより形成され、トランスファーモールド時の工程温度は例えば180℃である。接着層4としては、弾性率が高すぎると、トランスファーモールド時に樹脂から圧力を受けた場合に、配線基板1表面の凹凸に馴染む形への変形が十分に進まないため、ある程度以下の弾性率であることが好ましい。具体的には、トランスファーモールドの工程温度における接着層4の弾性率が1GPa以下であることが好ましい。特に、半導体装置の薄型化のために、接着層4の厚さが25μm以下と薄型化されている場合には、適当な弾性率を有する接着層4の選択は重要となる。以上の工程により、本実施の形態に係る半導体装置が製造される。
ここで、接着層4としてペースト状のものを用いると、チップ5と配線基板1との間から接着層4がはみ出し易いという問題がある。特に、チップ5の端と配線基板1上のCu配線2との間隔を0.5mm以下とする場合、はみ出した接着層4が配線基板1上のCu配線2に達して不良を生じる原因となる。また、チップ5として、チップ厚が100μm以下のものを用いた場合、はみ出した接着層4がチップ5上に這い上がって不良を生じる原因となる。そこで、接着層4としてフィルム状のものを用いるのが好ましい。
そして、フィルム状の接着層4を用いる場合、複数のチップ5が形成されたウェハの裏面に接着層4を貼り付けた後に、チップ5ごとにウェハを切断することで、製造工程を簡略化することができる。また、弾性率を高くするために、接着層4として、シリカフィラーやBNフィラー等の無機フィラーが10wt%以上、好ましくは50wt%以上含有するものを用いる。
また、配線基板1表面の凹部とチップとの隙間に空気が残るとボイドとなる。このボイドによるチップ5の割れを防ぐためには、最終形態でのチップ5下におけるボイドの割合を1割以下にする必要がある。そこで、図19に示すように、配線基板1としてチップ5を接着する表面領域においてCu配線2がある部分が90%以上のものを用いる。チップ5を接着する領域の配線としては、フローティング電位のダミー配線パターンや、電源電位もしくは接地電位電極と接続する電源/GND配線パターンの幅を、信号用配線の幅に比べて広く形成する事によってその領域を調整するのが好ましい。また、信号用配線の幅は、これら幅広配線に比べて、細く、ほぼ均一にすることにより、スタブ配線の形成や、インピーダンスの不整合によるノイズ源の形成などを防ぐことができる。チップ下領域の幅広配線パターン形状としては、図19に示すように、チップ外の領域に連続するスリットが形成されていることが好ましい。チップ外の領域に連続する放射状のスリットが形成されていることにより、チップの下に取り残されたボイドを効果的にチップ外に排出することができる。
また、配線基板1として表面の凹凸の深さが10μm以下、より好ましくは2μm以下のものを用いることにより、配線基板1の表面の凹部に接着層4が入り込み易くなるため、チップ5と配線基板1の接合強度を更に向上させることができる。配線基板1表面の凹凸の深さを低くする手段としては、例えば、ソルダーレジストを2層に分けて塗布する方法や、ドライフィルムレジストを使用し、ラミネートローラーによる熱圧着によって形成する方法などが選択可能である。
配線基板全体を示す平面図である。 配線基板を示す平面図である。 配線基板を示す断面図である。 図3に示す配線基板の要部を拡大した断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 図6に示す半導体装置の要部を拡大した断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 ワイヤボンディング工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す平面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。 図17に示す半導体装置の要部を拡大した断面図である。 チップを接着する表面領域においてCu配線がある部分が90%以上の配線基板を示す平面図である。
符号の説明
1 配線基板
2 Cu配線(配線)
4 接着層
5 チップ
10 金ワイヤ(ワイヤ)
11 パッド
16 樹脂

Claims (1)

  1. 配線基板上に接着層を介してチップを接着する接着工程と、
    前記接着工程の後に、超音波振動を印加しながら前記チップ上のパッドにワイヤをボンディングするワイヤボンディング工程とを有し、
    前記接着層は、前記チップの裏面と同一平面形状を有するフィルム状の接着層であり、かつ、前記ワイヤボンディング工程におけるプロセス温度での弾性率が100MPa以上であり、
    前記配線基板は、その表面に形成されたCu配線パターンと前記Cu配線パターンを覆うように形成されたソルダレジスト膜を有し、
    前記チップは、前記Cu配線パターン上の前記ソルダレジスト膜に接着され、前記チップの接着領域において、前記Cu配線パターンは、90%以上の占有率であり、
    前記Cu配線パターンは、複数の信号配線パターンと、前記複数の信号配線パターンを平面的に囲むように隣接して形成され、かつ、前記複数の信号配線パターンよりも幅の広い電源/GNDパターンを有し、
    前記電源/GNDパターンは、前記チップの接着領域の中心から外側の領域に連続するスリットを有することを特徴とする半導体装置の製造方法。
JP2006021029A 2006-01-30 2006-01-30 半導体装置の製造方法 Expired - Fee Related JP4984552B2 (ja)

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