JP4979399B2 - 半導体層構造及び半導体層構造の製造方法 - Google Patents
半導体層構造及び半導体層構造の製造方法 Download PDFInfo
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Description
N.H. Zhang他著、Journal of Crystal Growth 280,346−351(2005) Hobart他著、Journal of Electronic Materials 29(7),897−900(2000)
a)半導体材料からなる基板を準備する工程、
b)前記基板上に第二の半導体材料からなる層を施与して、半導体構造を作製する工程、
c)該半導体層構造中に軽ガスイオンを注入して、半導体層構造内に空洞を含む層を作製する工程、
d)前記空洞を規定種の不純物原子によって安定化する工程、
e)該半導体層構造上に少なくとも1層のエピタキシャル層を施与する工程
を含む方法によって解決される。
低い注入温度と高いドーズ量とを選択した場合に、注入直後に既にある一定の大きさの空洞が作製される。
この場合に、前記の層は、その使用目的に相応して当然のように任意の種類の不純物原子でドープされていてよい。
Claims (27)
- 以下の工程:
a)半導体材料からなる基板(1)を準備する工程、
b)前記基板(1)上に第二の半導体材料からなる層(2)を施与して、半導体層構造を作製する工程、
c)該半導体層構造中に水素及び希ガスからなる群から選択される1種又は複数種の原子種のガスイオンを注入して、その半導体層構造中に空洞を含む層(4)を作製する工程、
d)該半導体層構造上に少なくとも1層のエピタキシャル層(6)を施与する工程、
を含む半導体層構造の製造方法において、
基板(1)がシリコン基板又はシリコン層を含む基板であり、かつ層(2)が、炭素イオンを基板(1)中に注入することによって埋設されたシリコンカーバイド層を、表面に露出させることにより作製され、酸素、窒素及び炭素の群から選択される1種又は複数種の原子種の不純物原子を、高くとも5×1017cm−2のドーズ量で半導体層構造中に注入して、ガス注入によって作製された層(4)中の空洞を熱的に安定化することを特徴とする半導体層構造の製造方法。 - 請求項1記載の方法において、工程a)で準備される基板(1)が単結晶シリコンからなるウェハであることを特徴とする方法。
- 請求項1記載の方法において、工程a)で準備される基板(1)がSOIウェハであることを特徴とする方法。
- 請求項1から3までのいずれか1項記載の方法において、工程d)で施与される少なくとも1層のエピタキシャル層(6)が、基板(1)の半導体材料とは異なる熱膨張係数を
有する半導体材料を含むことを特徴とする方法。 - 請求項4記載の方法において、工程d)で施与される少なくとも1層のエピタキシャル層(6)が窒化物化合物半導体を含むことを特徴とする方法。
- 請求項1から5までのいずれか1項記載の方法において、工程c)におけるガスイオンの注入に際して、希ガスイオンが、ヘリウム、ネオン及びアルゴンの群から選択されることを特徴とする方法。
- 請求項1から6までのいずれか1項記載の方法において、工程c)におけるガスイオンの注入に際して、注入エネルギーを、半導体層構造中に作製される空洞を含む層(4)が、施与された層(2)と基板(1)との間の境界面より下方に存在するように選択することを特徴とする方法。
- 請求項1から7までのいずれか1項記載の方法において、工程c)におけるガスイオンの注入に際して、注入エネルギーを、半導体層構造中に作製される空洞を含む層(4)が、施与された層(2)の内部に存在するように選択することを特徴とする方法。
- 請求項1から8までのいずれか1項記載の方法において、酸素、窒素及び炭素の群から選択される1種又は複数種の原子種の不純物原子を注入する前に、半導体層構造の熱処理を少なくとも600℃の温度で実施することを特徴とする方法。
- 請求項1から9までのいずれか1項記載の方法において、前記層(2)が、炭素イオンを基板(1)の規定の深度に注入し、該基板(1)が、シリコンウェハであり、次いでこれを熱処理し、それにより基板(1)中に埋設された単結晶シリコンカーバイド層(2)と当該単結晶層の上方及び下方に遷移領域が形成され、引き続き上部基板層と当該単結晶層(2)上にある遷移領域とを除去し、それにより単結晶シリコンカーバイド層(2)を表面に露出させたものであることを特徴とする方法。
- シリコンからなる基板又はシリコン層を有する基板であってその上にシリコンカーバイドからなる層(2)が存在する基板(1)と、更に酸素、窒素及び炭素からなる群から選択される1種又は複数種の不純物原子で富化された領域であって層(2)中か又は層(2)と基板(1)との間の境界面より下方の規定の深度のいずれかに存在しシリコンカーバイド析出物を含む領域(3)と、更に不純物原子で富化された領域(3)の内部にある層であって水素気泡及び/又は希ガス気泡の形の空洞を含む層(4)と、更に少なくとも1層のエピタキシャル層であって層(2)上に施与されている層(6)と、空洞を含む層(4)の内部にある転位及び積層欠陥からなる欠陥領域(5)と、を含む半導体層構造であって、少なくとも1層のエピタキシャル層(6)が亀裂を有さず、かつ少なくとも1層のエピタキシャル層(6)の残留応力が1GPa以下である半導体層構造。
- 請求項11記載の半導体層構造であって、少なくとも1層のエピタキシャル層(6)の残留応力が370MPa以下であることを特徴とする半導体層構造。
- 請求項11又は12記載の半導体層構造であって、少なくとも1層のエピタキシャル層(6)の粗度が0.5〜7.0nmRMSである半導体層構造。
- 請求項13記載の半導体層構造であって、少なくとも1層のエピタキシャル層(6)の粗度が0.5〜2.0nmRMSである半導体層構造。
- 請求項11から14までのいずれか1項記載の半導体層構造であって、基板(1)が単結晶シリコンからなるウェハであることを特徴とする半導体層構造。
- 請求項11から14までのいずれか1項記載の半導体層構造であって、基板(1)がSOIウェハであることを特徴とする半導体層構造。
- 請求項11から16までのいずれか1項記載の半導体層構造であって、少なくとも1層のエピタキシャル層(6)が、基板(1)の半導体材料とは異なる熱膨張係数を有する半導体材料を含むことを特徴とする半導体層構造。
- 請求項17記載の半導体層構造であって、少なくとも1層のエピタキシャル層(6)が窒化物化合物半導体を含むことを特徴とする半導体層構造。
- 請求項18記載の半導体層構造であって、半導体層構造上に、窒化物化合物半導体を含む更なるエピタキシャル層(7)が施与されていることを特徴とする半導体層構造。
- 請求項19記載の半導体層構造であって、層(6)が窒化アルミニウムを含むことを特徴とする半導体層構造。
- 請求項20記載の半導体層構造であって、層(7)が窒化ガリウムを含むことを特徴とする半導体層構造。
- 請求項11から21までのいずれか1項記載の半導体層構造であって、高解像度X線回折によって測定される層(2)中のシリコンカーバイドの格子定数の相対膨張率が0.2%以下である半導体層構造。
- 請求項22記載の半導体層構造であって、基板(1)が、100mm以上の直径を有する半導体層構造。
- 請求項22記載の半導体層構造であって、シリコンカーバイドからなる層(2)が、基板(1)の表面より下方に存在する半導体層構造。
- 請求項11から24までのいずれか1項記載の半導体構造であって、層(2)の中又はその下方にある転位を含む欠陥領域(5)を含む半導体層構造。
- 請求項18から21までのいずれか1項記載の半導体層構造であって、更に、層(2)と窒化物化合物半導体を含む少なくとも1層のエピタキシャル層(6)との間に存在する1つ又は複数のエピタキシャル中間層を含む半導体層構造。
- 請求項18から26までのいずれか1項記載の半導体層構造上に作製された半導体素子であって、賦活化により0.1eV以上で7eV以下のエネルギーの光を放出する半導体素子。
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