JP4948785B2 - シリコン単結晶基板中に、ｍｏｓｆｅｔデバイスのための接合を形成するための方法 - Google Patents

シリコン単結晶基板中に、ｍｏｓｆｅｔデバイスのための接合を形成するための方法 Download PDF

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JP4948785B2
JP4948785B2 JP2005147746A JP2005147746A JP4948785B2 JP 4948785 B2 JP4948785 B2 JP 4948785B2 JP 2005147746 A JP2005147746 A JP 2005147746A JP 2005147746 A JP2005147746 A JP 2005147746A JP 4948785 B2 JP4948785 B2 JP 4948785B2
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polycrystalline
germanium
silicon
vapor deposition
chemical vapor
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JP2005340816A (ja
JP2005340816A5 (enExample
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ケヴィン・コック・チャン
ロバート・ジェイ・ミラー
エリン・シー・ジョーンズ
アトゥル・アジュメーラ
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International Business Machines Corp
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
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    • H01L21/02494—Structure
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2005147746A 2004-05-21 2005-05-20 シリコン単結晶基板中に、ｍｏｓｆｅｔデバイスのための接合を形成するための方法 Expired - Fee Related JP4948785B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/851,821 US7135391B2 (en) 2004-05-21 2004-05-21 Polycrystalline SiGe junctions for advanced devices
US10/851,821 2004-05-21

Publications (3)

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JP2005340816A JP2005340816A (ja) 2005-12-08
JP2005340816A5 JP2005340816A5 (enExample) 2008-05-15
JP4948785B2 true JP4948785B2 (ja) 2012-06-06

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JP2005147746A Expired - Fee Related JP4948785B2 (ja) 2004-05-21 2005-05-20 シリコン単結晶基板中に、ｍｏｓｆｅｔデバイスのための接合を形成するための方法

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Country Link
US (3) US7135391B2 (enExample)
JP (1) JP4948785B2 (enExample)
CN (1) CN100369199C (enExample)
TW (1) TWI346974B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8476220B2 (en) 1998-07-21 2013-07-02 Denis Barritault Biocompatible polymers, process for their preparation and compositions containing them

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US8323157B2 (en) * 2004-02-24 2012-12-04 Total Gym Global Corp. Method of using an exercise device having an adjustable incline
US7135391B2 (en) * 2004-05-21 2006-11-14 International Business Machines Corporation Polycrystalline SiGe junctions for advanced devices
NO324539B1 (no) * 2005-06-14 2007-11-19 Thin Film Electronics Asa Fremgangsmate i fabrikasjonen av en ferroelektrisk minneinnretning
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US20080124874A1 (en) * 2006-11-03 2008-05-29 Samsung Electronics Co., Ltd. Methods of Forming Field Effect Transistors Having Silicon-Germanium Source and Drain Regions
JP2009043916A (ja) 2007-08-08 2009-02-26 Toshiba Corp 半導体装置及びその製造方法
DE102007052626B4 (de) 2007-11-05 2018-05-30 Robert Bosch Gmbh Verfahren zur Herstellung von porösen Strukturen in auf Silizium basierenden Halbleiterstrukturen
US9095506B2 (en) * 2008-11-17 2015-08-04 Allergan, Inc. Biodegradable alpha-2 agonist polymeric implants and therapeutic uses thereof
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
JP2013089889A (ja) * 2011-10-21 2013-05-13 Elpida Memory Inc 半導体装置及びその製造方法
US8741726B2 (en) * 2011-12-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Reacted layer for improving thickness uniformity of strained structures
US11575043B1 (en) * 2021-07-23 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method of the same

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JPS57128022A (en) * 1981-01-30 1982-08-09 Tadatsugu Ito Forming method for silicon epitaxially grown film
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US6872626B1 (en) * 2003-11-21 2005-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a source/drain and a transistor employing the same
US7135391B2 (en) * 2004-05-21 2006-11-14 International Business Machines Corporation Polycrystalline SiGe junctions for advanced devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8476220B2 (en) 1998-07-21 2013-07-02 Denis Barritault Biocompatible polymers, process for their preparation and compositions containing them

Also Published As

Publication number Publication date
TWI346974B (en) 2011-08-11
US7741165B2 (en) 2010-06-22
JP2005340816A (ja) 2005-12-08
US20080248635A1 (en) 2008-10-09
CN1707754A (zh) 2005-12-14
US20070010076A1 (en) 2007-01-11
US20050260832A1 (en) 2005-11-24
US7387924B2 (en) 2008-06-17
US7135391B2 (en) 2006-11-14
CN100369199C (zh) 2008-02-13
TW200539323A (en) 2005-12-01

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