JP4898892B2 - 多勾配ドレインドーピング特性を持つ高電圧縦型トランジスタ - Google Patents
多勾配ドレインドーピング特性を持つ高電圧縦型トランジスタ Download PDFInfo
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- 238000005530 etching Methods 0.000 description 8
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 1
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Description
本出願は、2003年3月21日に出願された米国特許出願第10/393,759号の一部継続(CIP)出願であり、この米国特許出願第10/393,759号は、現在米国特許第6,573,558号である2001年9月7日に出願された米国特許出願第09/948,930号の継続出願であり、これらの出願の両方とも、本一部継続出願の代理人に割り当てられたものである。
拡張ドレイン又はドリフト領域を持つ高電圧電界効果トランジスタ(HVFET)、及び、それを作成する方法を説明する。HVFETは、低い固有オン状態抵抗を持ち、オフ状態で、高い電圧をサポートする。以下の説明では、本発明の完全な理解を提供するために、材料の型、ドーピングレベル、構造的特徴、処理ステップ等のような多数の具体的な詳細が示されている。半導体技術分野の当業者は、これらの詳細の多くがなくても、本発明を実践することができることを理解するであろう。他の例では、本発明を不明瞭にするのを避けるため、よく知られた要素、技術、及び処理ステップは、詳細に説明していない。
21 N+基板
22a N-型ドリフト領域
22b N-型ドリフト領域
24a フィールドプレート
24b フィールドプレート
24c フィールドプレート
26a P本体
26b P本体
26c P本体
26d P本体
27a N+
27b N+
27c N+
27d N+
28a 酸化物層
28b 酸化物層
28c 酸化物層
28d 酸化物層
29a ゲート酸化膜
29b ゲート酸化膜
30a ゲート
30b ゲート
31 ドレイン電極
32 ソース電極
33 絶縁層
40 ラテラルNMOS高電圧トランジスタ
41 N+基板
42a N-型ドリフト領域
42b N-型ドリフト領域
43 N+
44a フィールドプレート
44b フィールドプレート
45 ドレイン電極
46 ソース電極
47 N+
48 P本体
49a 酸化物層
49b 酸化物層
50 酸化物層
53 ゲート酸化膜
55 ゲート
56 ゲート電極
57 基板電極
60 ラテラルHVFETトランジスタ
61 N+基板
62a N-型ドリフト領域
63 N+
64a フィールドプレート
64b フィールドプレート
64c フィールドプレート
65 ドレイン電極
66 ソース電極
67 N+
68 P本体
69a 酸化物層
69b 酸化物層
69c 酸化物層
70 絶縁層
73 ゲート酸化膜
75 ゲート
77 基板電極
80 縦型HVFETトランジスタ
81 N+基板
82a N-型ドリフト領域
82b N-型ドリフト領域
84a フィールドプレート部材
84b フィールドプレート部材
84c フィールドプレート部材
86a P本体
86b P本体
87a N+領域
87b N+領域
87c N+領域
87d N+領域
88a 酸化物層
88b 酸化物層
88c 酸化物層
89a ゲート酸化膜
90a ゲート
90b ゲート
90c ゲート
90d ゲート
91 ドレイン電極
92 ソース電極
100 N+基板
101 Epi
102a Ox
102b Ox
103a FP
103b FP
105 N+
106 誘電体層
107 P本体
109 ソース
110a FP
110b FP
111 ドレイン
112a 溝
112b 溝
113a ゲート
113b ゲート
115a MOSゲート
115b MOSゲート
116a 誘電体層
116b 誘電体層
120 グラフ
121 グラフ
123 グラフ
125 グラフ
126 グラフ
Claims (18)
- パワートランジスタを製造する方法であって、
基板上にエピタキシャル層を形成する段階であって、当該エピタキシャル層及び当該半導体基板は第一の導電型であり、当該エピタキシャル層は少なくとも10%異なるそれぞれの第一及び第二のドーピング濃度勾配を有する第一及び第二の部分とともに形成され、第一及び第二の部分は前記エピタキシャル層の上面の下に形成され、第一の部分は第二の部分の上に形成され、第一及び第二の部分の各々においてドーピング濃度は前記上面からの距離とともに増加する、基板上にエピタキシャル層を形成する段階と、
第一及び第二の側壁を有するメサを画成するために、前記エピタキシャル層において、前記上面から前記基板へ垂直方向に下に向かって延在する第一及び第二の溝を形成する段階であって、前記第一及び第二の部分は前記メサのドリフト領域を備える、第一及び第二の溝を形成する段階と、
各溝を部分的に埋めるように前記第一及び第二の側壁の上に誘電体層を形成する段階と、
第一及び第二の溝の残りの部分を導電材料で埋める段階と、
前記メサの上部においてソースと本体領域を形成する段階であって、前記ソース領域は第一の導電型であり前記本体部分は第一の導電型の反対の第二の導電型であり、前記本体領域はソースを前記ドリフト領域の第一の部分から分離する、ソースと本体領域を形成する段階と、
前記本体領域に隣接する誘電体層内に埋設されるゲートを形成する段階と、
を備えることを特徴とする方法。 - さらに、前記ソース領域に接続されたソース電極を形成する段階と、
前記基板に接続されたドレイン電極を形成する段階と、
を備えることを特徴とする請求項1に記載の方法。 - 前記第一の導電型はn型を含み、前記第二の導電型はp型を含むことを特徴とする請求項1に記載の方法。
- 前記誘電体層は酸化物を含むことを特徴とする請求項1に記載の方法。
- 前記導電材料はドープされた多結晶シリコンを含むことを特徴とする請求項1に記載の方法。
- パワートランジスタを製造する方法であって、
ドーピング濃度勾配を伴うエピタキシャル層を形成する段階であって、前記ドーピング濃度勾配はエピタキシャル層の下部において変化し、当該下部におけるドーピング濃度勾配は前記エピタキシャル層の上面からの垂直距離とともに増加し、前記ドーピング濃度勾配は前記下部の最上部の付近から前記下部の底部付近で少なくとも10%異なる、エピタキシャル層を形成する段階と、
第一及び第二の横方向の側壁を有するメサを画成するために、前記エピタキシャル層において、前記上面から垂直方向に延在する第一及び第二の溝を形成する段階であって、前記下部は前記メサのドリフト領域を備える、第一及び第二の溝を形成する段階と、
前記メサの第一及び第二の側壁を誘電材料でカバーする段階と、
第一及び第二の溝において、第一及び第二のフィールドプレート部材を形成する段階であって、当該第一及び第二のフィールドプレート部材は誘電材料により前記メサから完全に絶縁された導電材料により形成される段階と、
前記メサの上部に横方向に隣接する前記誘電材料内に埋設された溝ゲート構造を形成する段階と、
を備えることを特徴とする方法。 - 前記エピタキシャル層は第一の導電型とともに形成されることを特徴とする請求項6に記載の方法。
- さらに、前記メサの上部において、ソース及び本体領域を形成する段階を備え、前記ソース領域は前記第一の導電型であり、前記本体領域は第一の導電型の反対の第二の導電型であり、前記本体領域は前記ドリフト領域の下部から前記ソースを分離することを特徴とする請求項7に記載の方法。
- パワートランジスタを製造する方法であって、
ドーピング濃度勾配をともなうエピタキシャル層を形成する段階であって、前記ドーピング濃度勾配は、前記エピタキシャル層の下部を通る垂直方向において前記下部の最上部付近から前記下部の底部付近で少なくとも10%変化し、前記ドーピング濃度勾配は前記エピタキシャル層の上面からの距離とともに増加する、エピタキシャル層を形成する段階と、
メサを画成するために、前記エピタキシャル層において、前記上面から垂直に延在する第一及び第二の溝を形成する段階であって、前記メサの下部はドリフト領域を備える、第一及び第二の溝を形成する段階と、
前記第一及び第二の溝において、それぞれ、第一及び第二のフィールドプレート部材を形成する段階であって、前記第一及び第二のフィールドプレート部材は誘電材料により前記メサから完全に絶縁された導電材料により形成される、第一及び第二のフィールドプレート部材を形成する段階と、
前記メサの上部にソース及び本体領域を形成する段階であって、前記ソース領域は第一の導電型であり、前記本体領域は第一の導電型と反対の第二の導電型であり、前記本体領域は前記ドリフト領域から前記ソースを分離し、前記ドリフト領域は第一の導電型である、ソース及び本体領域を形成する段階と、
前記本体領域に隣接する前記誘電材料内に埋設されるゲートを形成する段階と、
前記ソース領域を第一及び第二のフィールドプレート部材と電気的に接続する段階と、 を備えることを特徴とする方法。 - さらに、前記基板に接続されたドレイン電極を形成する段階を備える請求項9に記載の方法。
- 前記第一の導電型はn型を含み、前記第二の導電型はp型を含むことを特徴とする請求項9に記載の方法。
- 第一及び第二のフィールドプレート部材を形成する段階は、第一及び第二の溝の各々において前記誘電材料の層を形成する段階を備え、当該層は前記メサの第一及び第二の側壁部をカバーすることを特徴とする請求項9に記載の方法。
- 前記誘電材料は二酸化ケイ素を含むことを特徴とする請求項9に記載の方法。
- 前記導電材料はドープされた多結晶シリコンを含むことを特徴とする請求項9に記載の方法。
- 第一の導電型のドレイン領域と、
前記第一の導電型のソース領域と、
前記第一の導電型と反対の第二の導電型であり、前記ソース領域に隣接する本体領域と、
前記ドレイン領域から前記本体領域へ第一の方向に延在する前記第一の導電型のドリフト領域であって、それぞれ、各々が前記本体領域の下に配置され、各々が実質的に異なる第一及び第二のドーピング濃度勾配を有する第一及び第二の部分を備えるドリフト領域であって、第一及び第二の部分の第一及び第二のドーピング濃度勾配は、前記高電圧トランジスタのオフ状態のために最適化された第一の単一勾配ドーピング濃度特性及び前記高電圧トランジスタのオン状態のために最適化された第二の単一勾配ドーピング濃度特性の間であるドリフト領域と、
前記ドリフト領域の反対にそれぞれ配置される第一及び第二のフィールドプレート部材であって、前記ドリフト領域から完全に絶縁される第一及び第二のフィールドプレート部材と、
前記本体領域における前記ドリフト領域と前記ソース領域の間のチャネルを形成するために配置された絶縁されたゲートと、
を備える高電圧トランジスタ。 - 第一及び第二のドーピング濃度勾配は少なくとも10%異なることを特徴とする請求項15に記載の高電圧トランジスタ。
- 前記ドリフト領域はさらに、前記本体領域の真下に一定ドーピングの第三の部分を備えることを特徴とする請求項15に記載の高電圧トランジスタ。
- 第一及び第二の部分は前記ドリフト領域の中央付近で接触することを特徴とする請求項15に記載の高電圧トランジスタ。
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2005
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- 2005-05-26 JP JP2005154100A patent/JP4719507B2/ja active Active
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JP4719507B2 (ja) | 2011-07-06 |
US7221011B2 (en) | 2007-05-22 |
US7335944B2 (en) | 2008-02-26 |
EP1684357A2 (en) | 2006-07-26 |
US20080102581A1 (en) | 2008-05-01 |
US7459366B2 (en) | 2008-12-02 |
JP2010034602A (ja) | 2010-02-12 |
US20050133858A1 (en) | 2005-06-23 |
JP2011233910A (ja) | 2011-11-17 |
EP1684357A3 (en) | 2012-11-28 |
EP1684357B1 (en) | 2016-11-23 |
JP2006210869A (ja) | 2006-08-10 |
US20070132013A1 (en) | 2007-06-14 |
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