JP4886513B2 - フィーチャ微小寸法の低減 - Google Patents

フィーチャ微小寸法の低減 Download PDF

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Publication number
JP4886513B2
JP4886513B2 JP2006524669A JP2006524669A JP4886513B2 JP 4886513 B2 JP4886513 B2 JP 4886513B2 JP 2006524669 A JP2006524669 A JP 2006524669A JP 2006524669 A JP2006524669 A JP 2006524669A JP 4886513 B2 JP4886513 B2 JP 4886513B2
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Japan
Prior art keywords
deposition
gas
layer
photoresist
forming
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Expired - Fee Related
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JP2006524669A
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English (en)
Japanese (ja)
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JP2007503720A (ja
JP2007503720A5 (enExample
Inventor
カン・ショーン・エス．
リー・サンゲオン
チェン・ワン−リン
ハドソン・エリック・エー．
サジャディ・エス．・エム．・レザ
ザオ・ガン・ミン
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Lam Research Corp
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Lam Research Corp
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Publication of JP2007503720A5 publication Critical patent/JP2007503720A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

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  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2006524669A 2003-08-26 2004-07-29 フィーチャ微小寸法の低減 Expired - Fee Related JP4886513B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/648,953 US7250371B2 (en) 2003-08-26 2003-08-26 Reduction of feature critical dimensions
US10/648,953 2003-08-26
PCT/US2004/024853 WO2005024904A2 (en) 2003-08-26 2004-07-29 Reduction of feature critical dimensions

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011228441A Division JP2012019242A (ja) 2003-08-26 2011-10-18 フィーチャ微小寸法の低減

Publications (3)

Publication Number Publication Date
JP2007503720A JP2007503720A (ja) 2007-02-22
JP2007503720A5 JP2007503720A5 (enExample) 2008-02-14
JP4886513B2 true JP4886513B2 (ja) 2012-02-29

Family

ID=34216827

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2006524669A Expired - Fee Related JP4886513B2 (ja) 2003-08-26 2004-07-29 フィーチャ微小寸法の低減
JP2011228441A Withdrawn JP2012019242A (ja) 2003-08-26 2011-10-18 フィーチャ微小寸法の低減

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011228441A Withdrawn JP2012019242A (ja) 2003-08-26 2011-10-18 フィーチャ微小寸法の低減

Country Status (7)

Country Link
US (2) US7250371B2 (enExample)
JP (2) JP4886513B2 (enExample)
KR (1) KR101083622B1 (enExample)
CN (1) CN1922722B (enExample)
SG (1) SG149047A1 (enExample)
TW (1) TWI357094B (enExample)
WO (1) WO2005024904A2 (enExample)

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US7491647B2 (en) * 2005-03-08 2009-02-17 Lam Research Corporation Etch with striation control
US7539969B2 (en) * 2005-05-10 2009-05-26 Lam Research Corporation Computer readable mask shrink control processor
US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US7427458B2 (en) * 2005-06-30 2008-09-23 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US8529728B2 (en) * 2005-06-30 2013-09-10 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US20070181530A1 (en) * 2006-02-08 2007-08-09 Lam Research Corporation Reducing line edge roughness
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7429533B2 (en) 2006-05-10 2008-09-30 Lam Research Corporation Pitch reduction
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JP6050944B2 (ja) * 2012-04-05 2016-12-21 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマ処理装置
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JP6289996B2 (ja) * 2014-05-14 2018-03-07 東京エレクトロン株式会社 被エッチング層をエッチングする方法
US9543165B2 (en) * 2015-02-13 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
CN106154743B (zh) * 2015-03-24 2019-11-01 中芯国际集成电路制造(上海)有限公司 掩模及其形成方法
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WO2017171817A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Flowable dielectrics from vapor phase precursors
KR102476709B1 (ko) 2016-11-21 2022-12-09 나노스트링 테크놀로지스, 인크. 화학적 조성물 및 이것을 사용하는 방법
US10276398B2 (en) 2017-08-02 2019-04-30 Lam Research Corporation High aspect ratio selective lateral etch using cyclic passivation and etching
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10515815B2 (en) 2017-11-21 2019-12-24 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation
US10658174B2 (en) 2017-11-21 2020-05-19 Lam Research Corporation Atomic layer deposition and etch for reducing roughness
US10734238B2 (en) 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
US10446394B2 (en) 2018-01-26 2019-10-15 Lam Research Corporation Spacer profile control using atomic layer deposition in a multiple patterning process
CN108470678A (zh) * 2018-03-29 2018-08-31 德淮半导体有限公司 半导体结构及其形成方法
JP7077108B2 (ja) * 2018-04-05 2022-05-30 東京エレクトロン株式会社 被加工物の処理方法
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JPS63116430A (ja) * 1986-10-28 1988-05-20 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション マスク形成方法
JPH04282835A (ja) * 1991-03-11 1992-10-07 Fujitsu Ltd 半導体装置の製造方法
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Also Published As

Publication number Publication date
TWI357094B (en) 2012-01-21
US20050048785A1 (en) 2005-03-03
CN1922722A (zh) 2007-02-28
US7541291B2 (en) 2009-06-02
JP2007503720A (ja) 2007-02-22
TW200509213A (en) 2005-03-01
JP2012019242A (ja) 2012-01-26
WO2005024904A3 (en) 2006-06-15
US7250371B2 (en) 2007-07-31
KR20060126909A (ko) 2006-12-11
SG149047A1 (en) 2009-01-29
KR101083622B1 (ko) 2011-11-16
WO2005024904A2 (en) 2005-03-17
CN1922722B (zh) 2011-05-11
US20070293050A1 (en) 2007-12-20

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