KR101083622B1 - 피쳐 임계 치수의 감소 - Google Patents

피쳐 임계 치수의 감소 Download PDF

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Publication number
KR101083622B1
KR101083622B1 KR1020067004099A KR20067004099A KR101083622B1 KR 101083622 B1 KR101083622 B1 KR 101083622B1 KR 1020067004099 A KR1020067004099 A KR 1020067004099A KR 20067004099 A KR20067004099 A KR 20067004099A KR 101083622 B1 KR101083622 B1 KR 101083622B1
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KR
South Korea
Prior art keywords
layer
photoresist
feature
deposition
mask
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Expired - Fee Related
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KR1020067004099A
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English (en)
Korean (ko)
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KR20060126909A (ko
Inventor
션 에스 강
상헌 이
완-린 천
에릭 에이 허드슨
에스 엠 레자 사드자디
간 밍 자오
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램 리써치 코포레이션
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Publication of KR101083622B1 publication Critical patent/KR101083622B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020067004099A 2003-08-26 2004-07-29 피쳐 임계 치수의 감소 Expired - Fee Related KR101083622B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/648,953 2003-08-26
US10/648,953 US7250371B2 (en) 2003-08-26 2003-08-26 Reduction of feature critical dimensions
PCT/US2004/024853 WO2005024904A2 (en) 2003-08-26 2004-07-29 Reduction of feature critical dimensions

Publications (2)

Publication Number Publication Date
KR20060126909A KR20060126909A (ko) 2006-12-11
KR101083622B1 true KR101083622B1 (ko) 2011-11-16

Family

ID=34216827

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067004099A Expired - Fee Related KR101083622B1 (ko) 2003-08-26 2004-07-29 피쳐 임계 치수의 감소

Country Status (7)

Country Link
US (2) US7250371B2 (enExample)
JP (2) JP4886513B2 (enExample)
KR (1) KR101083622B1 (enExample)
CN (1) CN1922722B (enExample)
SG (1) SG149047A1 (enExample)
TW (1) TWI357094B (enExample)
WO (1) WO2005024904A2 (enExample)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060134917A1 (en) * 2004-12-16 2006-06-22 Lam Research Corporation Reduction of etch mask feature critical dimensions
US7271107B2 (en) * 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US7491647B2 (en) * 2005-03-08 2009-02-17 Lam Research Corporation Etch with striation control
US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
US7539969B2 (en) * 2005-05-10 2009-05-26 Lam Research Corporation Computer readable mask shrink control processor
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US8529728B2 (en) * 2005-06-30 2013-09-10 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US7427458B2 (en) * 2005-06-30 2008-09-23 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US20070181530A1 (en) * 2006-02-08 2007-08-09 Lam Research Corporation Reducing line edge roughness
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7429533B2 (en) * 2006-05-10 2008-09-30 Lam Research Corporation Pitch reduction
US7309646B1 (en) * 2006-10-10 2007-12-18 Lam Research Corporation De-fluoridation process
KR100842763B1 (ko) 2007-03-19 2008-07-01 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US8262920B2 (en) * 2007-06-18 2012-09-11 Lam Research Corporation Minimization of mask undercut on deep silicon etch
US7985681B2 (en) * 2007-06-22 2011-07-26 Micron Technology, Inc. Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device
JP5248902B2 (ja) 2007-10-11 2013-07-31 東京エレクトロン株式会社 基板処理方法
WO2009085597A2 (en) * 2007-12-21 2009-07-09 Lam Research Corporation Cd bias loading control with arc layer open
KR101573954B1 (ko) * 2007-12-21 2015-12-02 램 리써치 코포레이션 포토레지스트 더블 패터닝
CN102007570B (zh) * 2007-12-21 2013-04-03 朗姆研究公司 用高蚀刻速率抗蚀剂掩膜进行蚀刻
US20090286402A1 (en) * 2008-05-13 2009-11-19 Applied Materials, Inc Method for critical dimension shrink using conformal pecvd films
JP2009295790A (ja) * 2008-06-05 2009-12-17 Toshiba Corp パターン形成方法
US8748323B2 (en) * 2008-07-07 2014-06-10 Macronix International Co., Ltd. Patterning method
JP2010041028A (ja) * 2008-07-11 2010-02-18 Tokyo Electron Ltd 基板処理方法
US7772122B2 (en) * 2008-09-18 2010-08-10 Lam Research Corporation Sidewall forming processes
CN101794729B (zh) * 2009-02-02 2012-12-12 和舰科技(苏州)有限公司 一种通过蚀刻形成半导体结构中的通孔的方法
US8304175B2 (en) * 2009-03-25 2012-11-06 Macronix International Co., Ltd. Patterning method
CN101996937A (zh) * 2009-08-17 2011-03-30 上海宏力半导体制造有限公司 接触孔形成方法
US8574447B2 (en) * 2010-03-31 2013-11-05 Lam Research Corporation Inorganic rapid alternating process for silicon etch
US20110244263A1 (en) * 2010-04-02 2011-10-06 Peicheng Ku Patterning using electrolysis
US8304262B2 (en) * 2011-02-17 2012-11-06 Lam Research Corporation Wiggling control for pseudo-hardmask
JP5634313B2 (ja) 2011-03-29 2014-12-03 富士フイルム株式会社 レジストパターン形成方法およびそれを用いたパターン化基板の製造方法
KR20120120729A (ko) 2011-04-25 2012-11-02 에스케이하이닉스 주식회사 반도체장치의 금속패턴 제조 방법
US8450212B2 (en) 2011-06-28 2013-05-28 International Business Machines Corporation Method of reducing critical dimension process bias differences between narrow and wide damascene wires
JP6050944B2 (ja) * 2012-04-05 2016-12-21 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマ処理装置
US9252183B2 (en) * 2013-01-16 2016-02-02 Canon Kabushiki Kaisha Solid state image pickup apparatus and method for manufacturing the same
US8883648B1 (en) * 2013-09-09 2014-11-11 United Microelectronics Corp. Manufacturing method of semiconductor structure
CN104465386A (zh) * 2013-09-24 2015-03-25 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
GB201322931D0 (en) 2013-12-23 2014-02-12 Spts Technologies Ltd Method of etching
JP6289996B2 (ja) * 2014-05-14 2018-03-07 東京エレクトロン株式会社 被エッチング層をエッチングする方法
US9543165B2 (en) * 2015-02-13 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
CN106154743B (zh) * 2015-03-24 2019-11-01 中芯国际集成电路制造(上海)有限公司 掩模及其形成方法
US9543203B1 (en) 2015-07-02 2017-01-10 United Microelectronics Corp. Method of fabricating a semiconductor structure with a self-aligned contact
US9543148B1 (en) 2015-09-01 2017-01-10 Lam Research Corporation Mask shrink layer for high aspect ratio dielectric etch
US20190035673A1 (en) * 2016-03-31 2019-01-31 Intel Corporation Flowable dielectrics from vapor phase precursors
JP6730525B2 (ja) 2016-11-21 2020-07-29 ナノストリング テクノロジーズ，インコーポレイティド 化学組成物とそれを利用する方法
US10276398B2 (en) 2017-08-02 2019-04-30 Lam Research Corporation High aspect ratio selective lateral etch using cyclic passivation and etching
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10658174B2 (en) * 2017-11-21 2020-05-19 Lam Research Corporation Atomic layer deposition and etch for reducing roughness
US10734238B2 (en) 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
US10515815B2 (en) 2017-11-21 2019-12-24 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation
US10446394B2 (en) 2018-01-26 2019-10-15 Lam Research Corporation Spacer profile control using atomic layer deposition in a multiple patterning process
CN108470678A (zh) * 2018-03-29 2018-08-31 德淮半导体有限公司 半导体结构及其形成方法
JP7077108B2 (ja) * 2018-04-05 2022-05-30 東京エレクトロン株式会社 被加工物の処理方法
US10453684B1 (en) * 2018-05-09 2019-10-22 Applied Materials, Inc. Method for patterning a material layer with desired dimensions
EP3794146B1 (en) 2018-05-14 2025-12-10 Bruker Spatial Biology, Inc. Method for identifying a predetermined nucleotide sequence
JPWO2024203220A1 (enExample) * 2023-03-24 2024-10-03

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895740A (en) * 1996-11-13 1999-04-20 Vanguard International Semiconductor Corp. Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378170A (en) * 1976-12-22 1978-07-11 Toshiba Corp Continuous processor for gas plasma etching
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
US4871630A (en) * 1986-10-28 1989-10-03 International Business Machines Corporation Mask using lithographic image size reduction
US5273609A (en) * 1990-09-12 1993-12-28 Texas Instruments Incorporated Method and apparatus for time-division plasma chopping in a multi-channel plasma processing equipment
JPH04282835A (ja) * 1991-03-11 1992-10-07 Fujitsu Ltd 半導体装置の製造方法
JP2689031B2 (ja) * 1991-04-01 1997-12-10 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH0637072A (ja) * 1992-07-15 1994-02-10 Kawasaki Steel Corp テーパエッチング方法
DE4241045C1 (de) * 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
US5296410A (en) * 1992-12-16 1994-03-22 Samsung Electronics Co., Ltd. Method for separating fine patterns of a semiconductor device
JP3685832B2 (ja) * 1995-02-28 2005-08-24 ソニー株式会社 半導体装置の製造方法
GB9616225D0 (en) * 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
US6187685B1 (en) * 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US6218288B1 (en) * 1998-05-11 2001-04-17 Micron Technology, Inc. Multiple step methods for forming conformal layers
US6416933B1 (en) * 1999-04-01 2002-07-09 Advanced Micro Devices, Inc. Method to produce small space pattern using plasma polymerization layer
US6368974B1 (en) * 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
JP3589201B2 (ja) * 2001-07-02 2004-11-17 Ｔｄｋ株式会社 薄膜パターニング方法、薄膜デバイスの製造方法及び薄膜磁気ヘッドの製造方法
US6656282B2 (en) * 2001-10-11 2003-12-02 Moohan Co., Ltd. Atomic layer deposition apparatus and process using remote plasma
US6750150B2 (en) * 2001-10-18 2004-06-15 Macronix International Co., Ltd. Method for reducing dimensions between patterns on a photoresist
KR100448714B1 (ko) * 2002-04-24 2004-09-13 삼성전자주식회사 다층 나노라미네이트 구조를 갖는 반도체 장치의 절연막및 그의 형성방법
US6780708B1 (en) * 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
US7012027B2 (en) * 2004-01-27 2006-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Zirconium oxide and hafnium oxide etching using halogen containing chemicals
US20060134917A1 (en) 2004-12-16 2006-06-22 Lam Research Corporation Reduction of etch mask feature critical dimensions
US7273815B2 (en) 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895740A (en) * 1996-11-13 1999-04-20 Vanguard International Semiconductor Corp. Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers

Also Published As

Publication number Publication date
KR20060126909A (ko) 2006-12-11
US7250371B2 (en) 2007-07-31
JP2007503720A (ja) 2007-02-22
JP2012019242A (ja) 2012-01-26
SG149047A1 (en) 2009-01-29
CN1922722B (zh) 2011-05-11
CN1922722A (zh) 2007-02-28
US20050048785A1 (en) 2005-03-03
TWI357094B (en) 2012-01-21
TW200509213A (en) 2005-03-01
WO2005024904A2 (en) 2005-03-17
WO2005024904A3 (en) 2006-06-15
US7541291B2 (en) 2009-06-02
US20070293050A1 (en) 2007-12-20
JP4886513B2 (ja) 2012-02-29

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