CN1922722B - 减少图案特征的临界尺寸 - Google Patents

减少图案特征的临界尺寸 Download PDF

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Publication number
CN1922722B
CN1922722B CN2004800313250A CN200480031325A CN1922722B CN 1922722 B CN1922722 B CN 1922722B CN 2004800313250 A CN2004800313250 A CN 2004800313250A CN 200480031325 A CN200480031325 A CN 200480031325A CN 1922722 B CN1922722 B CN 1922722B
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China
Prior art keywords
layer
deposit
photoresist
feature
critical dimension
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Expired - Fee Related
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CN2004800313250A
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English (en)
Chinese (zh)
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CN1922722A (zh
Inventor
S·S·康
S·李
W·-L·陈
E·A·赫德森
S·M·R·萨德贾迪
G·M·赵
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Lam Research Corp
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Lam Research Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CN2004800313250A 2003-08-26 2004-07-29 减少图案特征的临界尺寸 Expired - Fee Related CN1922722B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/648,953 US7250371B2 (en) 2003-08-26 2003-08-26 Reduction of feature critical dimensions
US10/648,953 2003-08-26
PCT/US2004/024853 WO2005024904A2 (en) 2003-08-26 2004-07-29 Reduction of feature critical dimensions

Publications (2)

Publication Number Publication Date
CN1922722A CN1922722A (zh) 2007-02-28
CN1922722B true CN1922722B (zh) 2011-05-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004800313250A Expired - Fee Related CN1922722B (zh) 2003-08-26 2004-07-29 减少图案特征的临界尺寸

Country Status (7)

Country Link
US (2) US7250371B2 (enExample)
JP (2) JP4886513B2 (enExample)
KR (1) KR101083622B1 (enExample)
CN (1) CN1922722B (enExample)
SG (1) SG149047A1 (enExample)
TW (1) TWI357094B (enExample)
WO (1) WO2005024904A2 (enExample)

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US7491647B2 (en) * 2005-03-08 2009-02-17 Lam Research Corporation Etch with striation control
US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
US7539969B2 (en) * 2005-05-10 2009-05-26 Lam Research Corporation Computer readable mask shrink control processor
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US8529728B2 (en) * 2005-06-30 2013-09-10 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US7427458B2 (en) * 2005-06-30 2008-09-23 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US20070181530A1 (en) * 2006-02-08 2007-08-09 Lam Research Corporation Reducing line edge roughness
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7429533B2 (en) 2006-05-10 2008-09-30 Lam Research Corporation Pitch reduction
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Also Published As

Publication number Publication date
US7541291B2 (en) 2009-06-02
US7250371B2 (en) 2007-07-31
US20050048785A1 (en) 2005-03-03
SG149047A1 (en) 2009-01-29
TWI357094B (en) 2012-01-21
JP4886513B2 (ja) 2012-02-29
TW200509213A (en) 2005-03-01
WO2005024904A2 (en) 2005-03-17
KR20060126909A (ko) 2006-12-11
US20070293050A1 (en) 2007-12-20
JP2007503720A (ja) 2007-02-22
KR101083622B1 (ko) 2011-11-16
CN1922722A (zh) 2007-02-28
WO2005024904A3 (en) 2006-06-15
JP2012019242A (ja) 2012-01-26

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