JP4865564B2 - 誘電体レイヤにフィーチャをエッチングするための方法及び装置 - Google Patents

誘電体レイヤにフィーチャをエッチングするための方法及び装置 Download PDF

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Publication number
JP4865564B2
JP4865564B2 JP2006539644A JP2006539644A JP4865564B2 JP 4865564 B2 JP4865564 B2 JP 4865564B2 JP 2006539644 A JP2006539644 A JP 2006539644A JP 2006539644 A JP2006539644 A JP 2006539644A JP 4865564 B2 JP4865564 B2 JP 4865564B2
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Prior art keywords
etching
polymer
gas
photoresist
trench
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Expired - Fee Related
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JP2006539644A
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Japanese (ja)
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JP2007511096A5 (https=
JP2007511096A (ja
Inventor
ワッガナー・エリック
チュ・ヘレン・エイチ．
レ・ダニエル
ラーベンハルト・ピーター
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006539644A 2003-11-12 2004-11-03 誘電体レイヤにフィーチャをエッチングするための方法及び装置 Expired - Fee Related JP4865564B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/712,410 2003-11-12
US10/712,410 US6949460B2 (en) 2003-11-12 2003-11-12 Line edge roughness reduction for trench etch
PCT/US2004/036746 WO2005050700A2 (en) 2003-11-12 2004-11-03 Line edge roughness reduction for trench etch

Publications (3)

Publication Number Publication Date
JP2007511096A JP2007511096A (ja) 2007-04-26
JP2007511096A5 JP2007511096A5 (https=) 2008-04-24
JP4865564B2 true JP4865564B2 (ja) 2012-02-01

Family

ID=34552675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539644A Expired - Fee Related JP4865564B2 (ja) 2003-11-12 2004-11-03 誘電体レイヤにフィーチャをエッチングするための方法及び装置

Country Status (8)

Country Link
US (2) US6949460B2 (https=)
EP (1) EP1683194A4 (https=)
JP (1) JP4865564B2 (https=)
KR (1) KR101134327B1 (https=)
CN (1) CN100477135C (https=)
IL (1) IL175527A0 (https=)
TW (1) TWI351054B (https=)
WO (1) WO2005050700A2 (https=)

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US7358146B2 (en) * 2003-06-24 2008-04-15 Micron Technology, Inc. Method of forming a capacitor
US7153778B2 (en) * 2004-02-20 2006-12-26 Micron Technology, Inc. Methods of forming openings, and methods of forming container capacitors
JP2005314531A (ja) 2004-04-28 2005-11-10 Sony Corp ハイブリッドシリカポリマー、その製造方法およびプロトン伝導性材料
US7723235B2 (en) * 2004-09-17 2010-05-25 Renesas Technology Corp. Method for smoothing a resist pattern prior to etching a layer using the resist pattern
US7196014B2 (en) * 2004-11-08 2007-03-27 International Business Machines Corporation System and method for plasma induced modification and improvement of critical dimension uniformity
US7622393B2 (en) * 2005-11-04 2009-11-24 Tokyo Electron Limited Method and apparatus for manufacturing a semiconductor device, control program thereof and computer-readable storage medium storing the control program
US7556992B2 (en) * 2006-07-31 2009-07-07 Freescale Semiconductor, Inc. Method for forming vertical structures in a semiconductor device
US20080124937A1 (en) * 2006-08-16 2008-05-29 Songlin Xu Selective etching method and apparatus
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
US8026180B2 (en) * 2007-07-12 2011-09-27 Micron Technology, Inc. Methods of modifying oxide spacers
US8003522B2 (en) * 2007-12-19 2011-08-23 Fairchild Semiconductor Corporation Method for forming trenches with wide upper portion and narrow lower portion
WO2009085672A2 (en) 2007-12-21 2009-07-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US7998872B2 (en) * 2008-02-06 2011-08-16 Tokyo Electron Limited Method for etching a silicon-containing ARC layer to reduce roughness and CD
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
US8921726B2 (en) * 2009-02-06 2014-12-30 Lg Chem, Ltd. Touch screen and manufacturing method thereof
US8236700B2 (en) * 2009-08-17 2012-08-07 Tokyo Electron Limited Method for patterning an ARC layer using SF6 and a hydrocarbon gas
CN102041508B (zh) * 2009-10-23 2012-07-25 中芯国际集成电路制造(上海)有限公司 刻蚀沟槽的方法
JP5655296B2 (ja) * 2009-12-01 2015-01-21 セントラル硝子株式会社 エッチングガス
US8877641B2 (en) * 2009-12-28 2014-11-04 Spansion Llc Line-edge roughness improvement for small pitches
US20130078815A1 (en) * 2011-09-23 2013-03-28 Nanya Technology Corporation Method for forming semiconductor structure with reduced line edge roughness
CN103854995B (zh) * 2012-12-06 2016-10-19 中微半导体设备(上海)有限公司 一种改善侧壁条痕的刻蚀工艺及其装置
JP6239365B2 (ja) 2013-12-11 2017-11-29 東京エレクトロン株式会社 シリコン層をエッチングする方法
US10734228B2 (en) 2017-12-19 2020-08-04 Tokyo Electron Limited Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes
US11473191B2 (en) 2019-02-27 2022-10-18 Applied Materials, Inc. Method for creating a dielectric filled nanostructured silica substrate for flat optical devices

Citations (6)

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JPH05129244A (ja) * 1991-11-05 1993-05-25 Kokusai Electric Co Ltd プラズマエツチング方法及び装置
JPH11121598A (ja) * 1997-01-29 1999-04-30 Sony Corp 複合材料及びその製造方法、基体処理装置及びその作製方法、基体載置ステージ及びその作製方法、並びに基体処理方法
WO2002049089A1 (fr) * 2000-12-14 2002-06-20 Tokyo Electron Limited Methode de gravure d'un film isolant poreux, procede de double damasquinage, dispositif a semi-conducteur
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
JP2003195522A (ja) * 2001-12-26 2003-07-09 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
JP2003282550A (ja) * 2001-11-12 2003-10-03 Hynix Semiconductor Inc 半導体素子の製造方法

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US5658425A (en) 1991-10-16 1997-08-19 Lam Research Corporation Method of etching contact openings with reduced removal rate of underlying electrically conductive titanium silicide layer
US5976993A (en) * 1996-03-28 1999-11-02 Applied Materials, Inc. Method for reducing the intrinsic stress of high density plasma films
US6345589B1 (en) * 1996-03-29 2002-02-12 Applied Materials, Inc. Method and apparatus for forming a borophosphosilicate film
US5914202A (en) * 1996-06-10 1999-06-22 Sharp Microeletronics Technology, Inc. Method for forming a multi-level reticle
US6090304A (en) 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
US6080680A (en) 1997-12-19 2000-06-27 Lam Research Corporation Method and composition for dry etching in semiconductor fabrication
US6340435B1 (en) * 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
US6027861A (en) * 1998-03-20 2000-02-22 Taiwan Semiconductor Manufacturing Company VLSIC patterning process
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
KR100476845B1 (ko) * 1999-04-06 2005-03-17 동경 엘렉트론 주식회사 전극, 적재대, 플라즈마 처리 장치 및 전극과 적재대의제조 방법
US6444039B1 (en) * 2000-03-07 2002-09-03 Simplus Systems Corporation Three-dimensional showerhead apparatus
JP2001308065A (ja) * 2000-04-19 2001-11-02 Nec Corp ドライエッチング装置およびドライエッチング方法
US6403491B1 (en) * 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
US6518174B2 (en) 2000-12-22 2003-02-11 Lam Research Corporation Combined resist strip and barrier etch process for dual damascene structures
US20020121500A1 (en) * 2000-12-22 2002-09-05 Rao Annapragada Method of etching with NH3 and fluorine chemistries
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
US6786175B2 (en) * 2001-08-08 2004-09-07 Lam Research Corporation Showerhead electrode design for semiconductor processing reactor
US6495469B1 (en) * 2001-12-03 2002-12-17 Taiwan Semiconductor Manufacturing Company High selectivity, low etch depth micro-loading process for non stop layer damascene etch
CN1204606C (zh) * 2001-12-04 2005-06-01 联华电子股份有限公司 形成具有高深宽比的沟槽的蚀刻方法
US6867145B2 (en) 2001-12-17 2005-03-15 Hynix Semiconductor Inc. Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser
US6828251B2 (en) * 2002-02-15 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improved plasma etching control
CN100580562C (zh) * 2002-03-06 2010-01-13 旺宏电子股份有限公司 增进介电抗反射涂布层的光阻蚀刻选择比的方法
US6686293B2 (en) * 2002-05-10 2004-02-03 Applied Materials, Inc Method of etching a trench in a silicon-containing dielectric material
US6902648B2 (en) * 2003-01-09 2005-06-07 Oki Electric Industry Co., Ltd. Plasma etching device
US7316761B2 (en) * 2003-02-03 2008-01-08 Applied Materials, Inc. Apparatus for uniformly etching a dielectric layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129244A (ja) * 1991-11-05 1993-05-25 Kokusai Electric Co Ltd プラズマエツチング方法及び装置
JPH11121598A (ja) * 1997-01-29 1999-04-30 Sony Corp 複合材料及びその製造方法、基体処理装置及びその作製方法、基体載置ステージ及びその作製方法、並びに基体処理方法
WO2002049089A1 (fr) * 2000-12-14 2002-06-20 Tokyo Electron Limited Methode de gravure d'un film isolant poreux, procede de double damasquinage, dispositif a semi-conducteur
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
JP2003282550A (ja) * 2001-11-12 2003-10-03 Hynix Semiconductor Inc 半導体素子の製造方法
JP2003195522A (ja) * 2001-12-26 2003-07-09 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法

Also Published As

Publication number Publication date
CN100477135C (zh) 2009-04-08
US20050101126A1 (en) 2005-05-12
EP1683194A4 (en) 2008-06-25
EP1683194A2 (en) 2006-07-26
WO2005050700A2 (en) 2005-06-02
JP2007511096A (ja) 2007-04-26
IL175527A0 (en) 2006-09-05
US20050277289A1 (en) 2005-12-15
KR101134327B1 (ko) 2012-04-09
KR20060123312A (ko) 2006-12-01
CN1902745A (zh) 2007-01-24
WO2005050700A3 (en) 2005-12-01
US6949460B2 (en) 2005-09-27
TWI351054B (en) 2011-10-21
TW200524002A (en) 2005-07-16

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