TWI351054B - Line edge roughness reduction for trench etch - Google Patents

Line edge roughness reduction for trench etch

Info

Publication number
TWI351054B
TWI351054B TW093134334A TW93134334A TWI351054B TW I351054 B TWI351054 B TW I351054B TW 093134334 A TW093134334 A TW 093134334A TW 93134334 A TW93134334 A TW 93134334A TW I351054 B TWI351054 B TW I351054B
Authority
TW
Taiwan
Prior art keywords
line edge
edge roughness
trench etch
roughness reduction
reduction
Prior art date
Application number
TW093134334A
Other languages
English (en)
Chinese (zh)
Other versions
TW200524002A (en
Inventor
Eric D Wagganer
Helen H Zhu
Daniel Le
Peter Loewenhardt
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of TW200524002A publication Critical patent/TW200524002A/zh
Application granted granted Critical
Publication of TWI351054B publication Critical patent/TWI351054B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW093134334A 2003-11-12 2004-11-10 Line edge roughness reduction for trench etch TWI351054B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/712,410 US6949460B2 (en) 2003-11-12 2003-11-12 Line edge roughness reduction for trench etch

Publications (2)

Publication Number Publication Date
TW200524002A TW200524002A (en) 2005-07-16
TWI351054B true TWI351054B (en) 2011-10-21

Family

ID=34552675

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093134334A TWI351054B (en) 2003-11-12 2004-11-10 Line edge roughness reduction for trench etch

Country Status (8)

Country Link
US (2) US6949460B2 (https=)
EP (1) EP1683194A4 (https=)
JP (1) JP4865564B2 (https=)
KR (1) KR101134327B1 (https=)
CN (1) CN100477135C (https=)
IL (1) IL175527A0 (https=)
TW (1) TWI351054B (https=)
WO (1) WO2005050700A2 (https=)

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US7153778B2 (en) * 2004-02-20 2006-12-26 Micron Technology, Inc. Methods of forming openings, and methods of forming container capacitors
JP2005314531A (ja) 2004-04-28 2005-11-10 Sony Corp ハイブリッドシリカポリマー、その製造方法およびプロトン伝導性材料
US7723235B2 (en) * 2004-09-17 2010-05-25 Renesas Technology Corp. Method for smoothing a resist pattern prior to etching a layer using the resist pattern
US7196014B2 (en) * 2004-11-08 2007-03-27 International Business Machines Corporation System and method for plasma induced modification and improvement of critical dimension uniformity
US7622393B2 (en) * 2005-11-04 2009-11-24 Tokyo Electron Limited Method and apparatus for manufacturing a semiconductor device, control program thereof and computer-readable storage medium storing the control program
US7556992B2 (en) * 2006-07-31 2009-07-07 Freescale Semiconductor, Inc. Method for forming vertical structures in a semiconductor device
US20080124937A1 (en) * 2006-08-16 2008-05-29 Songlin Xu Selective etching method and apparatus
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
US8026180B2 (en) * 2007-07-12 2011-09-27 Micron Technology, Inc. Methods of modifying oxide spacers
US8003522B2 (en) * 2007-12-19 2011-08-23 Fairchild Semiconductor Corporation Method for forming trenches with wide upper portion and narrow lower portion
WO2009085672A2 (en) 2007-12-21 2009-07-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US7998872B2 (en) * 2008-02-06 2011-08-16 Tokyo Electron Limited Method for etching a silicon-containing ARC layer to reduce roughness and CD
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
US8921726B2 (en) * 2009-02-06 2014-12-30 Lg Chem, Ltd. Touch screen and manufacturing method thereof
US8236700B2 (en) * 2009-08-17 2012-08-07 Tokyo Electron Limited Method for patterning an ARC layer using SF6 and a hydrocarbon gas
CN102041508B (zh) * 2009-10-23 2012-07-25 中芯国际集成电路制造(上海)有限公司 刻蚀沟槽的方法
JP5655296B2 (ja) * 2009-12-01 2015-01-21 セントラル硝子株式会社 エッチングガス
US8877641B2 (en) * 2009-12-28 2014-11-04 Spansion Llc Line-edge roughness improvement for small pitches
US20130078815A1 (en) * 2011-09-23 2013-03-28 Nanya Technology Corporation Method for forming semiconductor structure with reduced line edge roughness
CN103854995B (zh) * 2012-12-06 2016-10-19 中微半导体设备(上海)有限公司 一种改善侧壁条痕的刻蚀工艺及其装置
JP6239365B2 (ja) 2013-12-11 2017-11-29 東京エレクトロン株式会社 シリコン層をエッチングする方法
US10734228B2 (en) 2017-12-19 2020-08-04 Tokyo Electron Limited Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes
US11473191B2 (en) 2019-02-27 2022-10-18 Applied Materials, Inc. Method for creating a dielectric filled nanostructured silica substrate for flat optical devices

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JPH05129244A (ja) * 1991-11-05 1993-05-25 Kokusai Electric Co Ltd プラズマエツチング方法及び装置
US5976993A (en) * 1996-03-28 1999-11-02 Applied Materials, Inc. Method for reducing the intrinsic stress of high density plasma films
US6345589B1 (en) * 1996-03-29 2002-02-12 Applied Materials, Inc. Method and apparatus for forming a borophosphosilicate film
US5914202A (en) * 1996-06-10 1999-06-22 Sharp Microeletronics Technology, Inc. Method for forming a multi-level reticle
JP4022954B2 (ja) * 1997-01-29 2007-12-19 ソニー株式会社 複合材料及びその製造方法、基体処理装置及びその作製方法、基体載置ステージ及びその作製方法、並びに基体処理方法
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US6080680A (en) 1997-12-19 2000-06-27 Lam Research Corporation Method and composition for dry etching in semiconductor fabrication
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US6444039B1 (en) * 2000-03-07 2002-09-03 Simplus Systems Corporation Three-dimensional showerhead apparatus
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JPWO2002049089A1 (ja) * 2000-12-14 2004-04-15 東京エレクトロン株式会社 多孔質絶縁膜のエッチング方法、デュアルダマシンプロセスおよび半導体装置
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US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
US6786175B2 (en) * 2001-08-08 2004-09-07 Lam Research Corporation Showerhead electrode design for semiconductor processing reactor
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
TWI276153B (en) * 2001-11-12 2007-03-11 Hynix Semiconductor Inc Method for fabricating semiconductor device
US6495469B1 (en) * 2001-12-03 2002-12-17 Taiwan Semiconductor Manufacturing Company High selectivity, low etch depth micro-loading process for non stop layer damascene etch
CN1204606C (zh) * 2001-12-04 2005-06-01 联华电子股份有限公司 形成具有高深宽比的沟槽的蚀刻方法
US6867145B2 (en) 2001-12-17 2005-03-15 Hynix Semiconductor Inc. Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser
JP3638266B2 (ja) * 2001-12-26 2005-04-13 株式会社半導体先端テクノロジーズ 半導体装置の製造方法
US6828251B2 (en) * 2002-02-15 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improved plasma etching control
CN100580562C (zh) * 2002-03-06 2010-01-13 旺宏电子股份有限公司 增进介电抗反射涂布层的光阻蚀刻选择比的方法
US6686293B2 (en) * 2002-05-10 2004-02-03 Applied Materials, Inc Method of etching a trench in a silicon-containing dielectric material
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Also Published As

Publication number Publication date
CN100477135C (zh) 2009-04-08
US20050101126A1 (en) 2005-05-12
EP1683194A4 (en) 2008-06-25
EP1683194A2 (en) 2006-07-26
WO2005050700A2 (en) 2005-06-02
JP4865564B2 (ja) 2012-02-01
JP2007511096A (ja) 2007-04-26
IL175527A0 (en) 2006-09-05
US20050277289A1 (en) 2005-12-15
KR101134327B1 (ko) 2012-04-09
KR20060123312A (ko) 2006-12-01
CN1902745A (zh) 2007-01-24
WO2005050700A3 (en) 2005-12-01
US6949460B2 (en) 2005-09-27
TW200524002A (en) 2005-07-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees