JP4746468B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4746468B2 JP4746468B2 JP2006112191A JP2006112191A JP4746468B2 JP 4746468 B2 JP4746468 B2 JP 4746468B2 JP 2006112191 A JP2006112191 A JP 2006112191A JP 2006112191 A JP2006112191 A JP 2006112191A JP 4746468 B2 JP4746468 B2 JP 4746468B2
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- insulating film
- charge storage
- storage layer
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- gate electrode
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
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- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
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- YKTSYUJCYHOUJP-UHFFFAOYSA-N [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] Chemical compound [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] YKTSYUJCYHOUJP-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
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- 239000012535 impurity Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000013076 target substance Substances 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
図1および図2は、それぞれ、本実施形態の第1および第2の不揮発性メモリセルのワード線方向(チャネル幅方向)の断面図である。図中、100は半導体基板、101はトンネル絶縁膜、102は浮遊ゲート電極、103はSTI(Shallow Trench Isolation)のための素子分離絶縁膜、104(1041 ,1042 ,1043 )はゲート電極間絶縁膜(以下、単に電極間絶縁膜という。)、105は制御ゲート電極を示している。
図14および図15は、それぞれ、本実施形態の第1および第2の不揮発性メモリセルのワード線方向(チャネル幅方向)の断面図である。なお、前出した図と同一符号は同一部分を示し、詳細な説明は省略する。
(第3の実施形態)
図22は、本実施形態の不揮発性メモリセルのビット線方向(チャネル長方向)の断面図である。
Claims (2)
- 半導体基板と、
前記半導体基板の表面に形成された素子分離溝内に埋め込まれた素子分離絶縁膜と、
前記半導体基板上に設けられた複数の不揮発性メモリセルと
を具備してなる半導体装置であって、
前記不揮発性メモリセルは、
前記半導体基板上に設けられた第1の絶縁膜と、
前記第1の絶縁膜上に設けられた電荷蓄積層と、
前記電荷蓄積層の上方に設けられた制御ゲート電極と、
前記制御ゲート電極と前記電荷蓄積層との間に設けられた第2の絶縁膜とを備え、
前記不揮発性メモリセルのチャネル幅方向の断面において、
前記素子分離絶縁膜の上面は、前記半導体基板の表面よりも高く、かつ、前記電荷蓄積層の上面よりも低く、
前記第2の絶縁膜は、前記素子分離絶縁膜の上面、前記電荷蓄積層の上面、および、前記電荷蓄積層の側面上に設けられており、
前記素子分離絶縁膜の上面上の前記第2の絶縁膜は、前記電荷蓄積層の上面上の前記第2の絶縁膜よりも誘電率が低く、かつ、前記電荷蓄積層の上面上の前記第2の絶縁膜とは組成が異なる第1の領域を含み、および
前記電荷蓄積層の側面上の前記第2の絶縁膜は、前記電荷蓄積層の上面上の前記第2の絶縁膜よりも誘電率が低く、かつ、前記第1の領域よりも誘電率が大きい第2の領域を含むことを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板の表面に形成された素子分離溝内に埋め込まれた素子分離絶縁膜と、
前記半導体基板上に設けられた複数の不揮発性メモリセルと
を具備してなる半導体装置であって、
前記不揮発性メモリセルは、
前記半導体基板上に設けられた第1の絶縁膜と、
前記第1の絶縁膜上に設けられた電荷蓄積層と、
前記電荷蓄積層の上方に設けられた制御ゲート電極と、
前記制御ゲート電極と前記電荷蓄積層との間に設けられ、金属酸化物を有する第2の絶縁膜とを備え、
前記不揮発性メモリセルのチャネル幅方向の断面において、
前記素子分離絶縁膜の上面は、前記半導体基板の表面よりも高く、かつ、前記電荷蓄積層の上面よりも低く、
前記第2の絶縁膜は、前記素子分離絶縁膜の上面、前記電荷蓄積層の上面、および、前記電荷蓄積層の側面上に設けられており、
前記素子分離絶縁膜の上面上の前記第2の絶縁膜は、前記電荷蓄積層の上面上の前記第2の絶縁膜よりも酸素組成が大きい金属酸化物からなる第1の領域を含み、および
前記電荷蓄積層の側面上の前記第2の絶縁膜は、前記電荷蓄積層の上面上の前記第2の絶縁膜よりも酸素組成が大きく、かつ、前記第1の領域よりも酸素組成が小さい第2の領域を含むことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006112191A JP4746468B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
US11/783,934 US7635890B2 (en) | 2006-04-14 | 2007-04-13 | Semiconductor device |
KR1020070036546A KR100908771B1 (ko) | 2006-04-14 | 2007-04-13 | 반도체 장치 |
KR1020090035875A KR101021378B1 (ko) | 2006-04-14 | 2009-04-24 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006112191A JP4746468B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011082842A Division JP2011135107A (ja) | 2011-04-04 | 2011-04-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007287858A JP2007287858A (ja) | 2007-11-01 |
JP4746468B2 true JP4746468B2 (ja) | 2011-08-10 |
Family
ID=38604036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006112191A Expired - Fee Related JP4746468B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7635890B2 (ja) |
JP (1) | JP4746468B2 (ja) |
KR (2) | KR100908771B1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4834517B2 (ja) * | 2006-11-09 | 2011-12-14 | 株式会社東芝 | 半導体装置 |
JP4855958B2 (ja) * | 2007-01-25 | 2012-01-18 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP2008192991A (ja) * | 2007-02-07 | 2008-08-21 | Toshiba Corp | 半導体装置 |
US8008707B2 (en) * | 2007-12-14 | 2011-08-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device provided with charge storage layer in memory cell |
JP2009253259A (ja) * | 2008-04-11 | 2009-10-29 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP5238332B2 (ja) * | 2008-04-17 | 2013-07-17 | 株式会社東芝 | 半導体装置の製造方法 |
JP2010045175A (ja) | 2008-08-12 | 2010-02-25 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP5398388B2 (ja) * | 2009-06-30 | 2014-01-29 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2012060086A (ja) | 2010-09-13 | 2012-03-22 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
WO2012077498A1 (ja) | 2010-12-06 | 2012-06-14 | 株式会社村田製作所 | 積層帯域通過フィルタ |
JP2011135107A (ja) * | 2011-04-04 | 2011-07-07 | Toshiba Corp | 半導体装置 |
JP2013021102A (ja) * | 2011-07-11 | 2013-01-31 | Toshiba Corp | 半導体記憶装置 |
US9082654B2 (en) | 2013-05-30 | 2015-07-14 | Rohm Co., Ltd. | Method of manufacturing non-volatile memory cell with simplified step of forming floating gate |
JP2014236015A (ja) * | 2013-05-30 | 2014-12-15 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
US20170256555A1 (en) * | 2016-03-07 | 2017-09-07 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing semiconductor device |
US10128265B2 (en) * | 2017-01-18 | 2018-11-13 | Micron Technology, Inc. | Memory cells, integrated structures and memory arrays |
Citations (4)
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JP2004281662A (ja) * | 2003-03-14 | 2004-10-07 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005026590A (ja) * | 2003-07-04 | 2005-01-27 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005235987A (ja) * | 2004-02-19 | 2005-09-02 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2005340853A (ja) * | 2005-07-11 | 2005-12-08 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
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JP2867782B2 (ja) * | 1992-03-17 | 1999-03-10 | 日本電気株式会社 | 半導体不揮発性記憶装置の製造方法 |
JP2001077333A (ja) | 1999-08-31 | 2001-03-23 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP4923318B2 (ja) | 1999-12-17 | 2012-04-25 | ソニー株式会社 | 不揮発性半導体記憶装置およびその動作方法 |
US6844604B2 (en) | 2001-02-02 | 2005-01-18 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
JP3964828B2 (ja) | 2003-05-26 | 2007-08-22 | 株式会社東芝 | 半導体装置 |
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JP4734019B2 (ja) | 2005-04-26 | 2011-07-27 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
KR100719366B1 (ko) * | 2005-06-15 | 2007-05-17 | 삼성전자주식회사 | 트렌치 소자분리막을 갖는 반도체 소자의 형성 방법 |
-
2006
- 2006-04-14 JP JP2006112191A patent/JP4746468B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-13 US US11/783,934 patent/US7635890B2/en not_active Expired - Fee Related
- 2007-04-13 KR KR1020070036546A patent/KR100908771B1/ko not_active IP Right Cessation
-
2009
- 2009-04-24 KR KR1020090035875A patent/KR101021378B1/ko not_active IP Right Cessation
Patent Citations (4)
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JP2004281662A (ja) * | 2003-03-14 | 2004-10-07 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005026590A (ja) * | 2003-07-04 | 2005-01-27 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005235987A (ja) * | 2004-02-19 | 2005-09-02 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2005340853A (ja) * | 2005-07-11 | 2005-12-08 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20070102432A (ko) | 2007-10-18 |
US20070241389A1 (en) | 2007-10-18 |
US7635890B2 (en) | 2009-12-22 |
KR20090046770A (ko) | 2009-05-11 |
KR100908771B1 (ko) | 2009-07-22 |
JP2007287858A (ja) | 2007-11-01 |
KR101021378B1 (ko) | 2011-03-14 |
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