JP4560818B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4560818B2 JP4560818B2 JP2005212419A JP2005212419A JP4560818B2 JP 4560818 B2 JP4560818 B2 JP 4560818B2 JP 2005212419 A JP2005212419 A JP 2005212419A JP 2005212419 A JP2005212419 A JP 2005212419A JP 4560818 B2 JP4560818 B2 JP 4560818B2
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- insulating film
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- chalcogenide layer
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010410 layer Substances 0.000 claims description 187
- 150000004770 chalcogenides Chemical group 0.000 claims description 148
- 230000015654 memory Effects 0.000 claims description 92
- 239000011229 interlayer Substances 0.000 claims description 40
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 14
- 239000013078 crystal Substances 0.000 description 7
- 238000001459 lithography Methods 0.000 description 7
- 239000012782 phase change material Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Description
2 カルコゲナイド層の相変化領域
3 カルコゲナイド層
4 上部電極
5 層間絶縁膜
6 埋め込み絶縁膜
7 コンタクト
8 第1絶縁膜
Claims (8)
- 相変化層をメモリセルの記憶素子として備えた半導体装置において、
ヒータ電極と、
前記ヒータ電極を覆う層間絶縁膜と、
前記ヒータ電極の上面に達するように前記層間絶縁膜に設けたコンタクトホールと、
前記コンタクトホール内において、前記コンタクトホールの側面に沿ってリング形状を有する前記相変化層と、
前記相変化層の内側面を覆い、前記コンタクトホール内を充填する埋め込み絶縁膜と、
前記相変化層の上面および前記埋め込み絶縁膜の上面を覆い、前記層間絶縁膜上に設けられた上部電極を備え、
前記コンタクトホール内において、前記相変化層の上面の位置は、前記層間絶縁膜及び前記埋め込み絶縁膜の上面の位置よりも低い位置に形成されていることを特徴とする半導体装置。 - 前記埋め込み絶縁膜は窒化膜であることを特徴とする請求項1に記載の半導体装置。
- 相変化層をメモリセルの記憶素子として備えた半導体装置において、
ヒータ電極と、
前記ヒータ電極を覆う層間絶縁膜と、
前記ヒータ電極の上面に達するように前記層間絶縁膜に設けたコンタクトホールと、
前記コンタクトホール内において、前記コンタクトホールの側面に沿ってリング形状を有する第1絶縁膜と、
前記第1絶縁膜の内側面を覆い、前記第1絶縁膜の内側面に沿ってリング形状を有する前記相変化層と、
前記相変化層の内側面を覆い、前記コンタクトホール内を充填する埋め込み絶縁膜と、
前記相変化層の上面と前記埋め込み絶縁膜の上面と前記第1絶縁膜の上面を覆い、前記層間絶縁膜上に設けられた上部電極を備え、
前記コンタクトホール内において、前記相変化層の上面の位置は、前記層間絶縁膜、前記埋め込み絶縁膜及び前記第1絶縁膜の上面の位置よりも低い位置に形成されていることを特徴とする半導体装置。 - 前記第1絶縁膜は窒化膜であることを特徴とする請求項3に記載の半導体装置。
- 前記相変化層は、カルコゲナイド層であることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 半導体基板上にヒータ電極を形成するヒータ電極形成工程と、
前記ヒータ電極上に層間絶縁膜を成膜し、該層間絶縁膜に前記ヒータ電極の上面に達するコンタクトホールを形成するコンタクト形成工程と、
前記コンタクトホールの内部を覆い、前記コンタクトホール内を完全には充填しない膜厚で相変化層を成膜する相変化層成膜工程と、
エッチバックを行って、前記層間絶縁膜上に成膜した前記相変化層を除去すると共に、前記コンタクトホール内に前記相変化層をサイドウォールとして形成する工程と、
前記コンタクトホール内を充填するように埋め込み絶縁膜を形成する埋め込み絶縁膜成膜工程と、
前記層間絶縁膜、前記埋め込み絶縁膜及び前記相変化層の表面を平坦化する平坦化工程と、
前記相変化層をエッチングし、前記相変化層の上面の位置を前記層間絶縁膜の上面の位置より低くするエッチング工程と、
前記相変化層及び前記埋め込み絶縁膜の上面に接触する上部電極を形成する工程と、を備えたことを特徴とする半導体装置の製造方法。 - 前記相変化層成膜工程の前に、第1の絶縁膜を成膜する成膜工程と、前記第1の絶縁膜をエッチバックする絶縁膜エッチバック工程とをさらに備え、
前記エッチング工程において、前記相変化層の上面の位置を前記第1の絶縁膜の上面の位置よりも低くすることを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記相変化層成膜工程は、カルコゲナイド材料を成膜することを特徴とする請求項6または7に記載の半導体装置の製造方法。
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