JP4560435B2 - 高性能計算システム及び高性能計算方法 - Google Patents
高性能計算システム及び高性能計算方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/803—Three-dimensional arrays or hypercubes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
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Description
S(N)=1/((FP/N)+FS)*(1−Fc*(1−RR/L);
である、アムダールの法則の派生形によって表す場合があり、S(N)=Nプロセッサでの高速化であり、Fp=並列コードの割合であり、Fs=非並列コードの割合であり、Fc=通信に充てられる処理の割合であり、RR/L=遠隔メモリ帯域幅の局所メモリ帯域幅に対する比率である。したがって、HPCシステム100が、処理性能にかなり等しいか、かなり近づいているI/O性能を備えることによって、HPCシステム100はHPCアプリケーションの全体効率を向上させ、システム管理の容易化を可能にする。
100 システム
102 HPCサーバ
104 インタフェース
105 管理ノード
106 ネットワーク
108 リンク
110 グリッド
115 ノード
120 局所クライアント
126 GUI
130 クラスタ管理エンジン
132 エージェント
140 ディスク・ファーム
142 ストレージ・クライアント
150 ジョブ
210 グリッド
215 グリッド
216 ノード・ライン
220 仮想クラスタ
230a ジョブ空間
230b ジョブ空間
315 ブレード
320a プロセッサ
320b プロセッサ
321 ノースブリッジ
322 サウスブリッジ
325 PCIチャネル
330a HT/PCIブリッジ
330b HT/PCIブリッジ
335a HCA
335b HCA
340a メモリ
340b メモリ
345 スイッチ
350a FPGA
350b FPGA
400a GUI
400b GUI
500 クラスタ管理エンジン
505 物理マネージャ
510 仮想マネージャ
515 ジョブ・スケジューラ
520 局所メモリ
521 物理リスト
522 仮想リスト
523 グループ・ファイル
524 ポリシー・テーブル
525 ジョブ・キュー
600 方法
605 工程
610 工程
615 工程
620 工程
625 工程
630 工程
635 判定工程
640 工程
645 工程
650 工程
655 工程
660 工程
665 工程
700 方法
705 工程
710 工程
715 工程
720 工程
725 判定工程
730 工程
735 工程
740 工程
745 工程
800 方法
805 工程
810 工程
815 判定工程
820 工程
825 工程
830 工程
835 工程
840 工程
845 工程
850 工程
Claims (24)
- HPCジョブを実行する高性能計算(HPC)システムであって、
HPCサーバを備え、前記HPCサーバは、ジョブを実行するよう動作可能な相互接続された複数のHPCノードを備え、前記複数のHPCノードを相互接続するグリッドを提供するよう動作可能であり、各HPCノードが、
マザーボードと、
8つ以上のポートを備えるスイッチであって、前記マザーボード上に統合され、前記複数のHPCノードの少なくとも部分集合を相互接続するよう動作可能なスイッチと、
前記ジョブを実行するよう動作可能な少なくとも2つのプロセッサであって、各プロセッサが、前記統合スイッチに通信可能に結合され、前記マザーボード上に統合されたプロセッサとを備え、
前記HPCサーバは、前記ジョブの実行において前記HPCノードを動的に割り当て、管理するよう動作可能なクラスタ管理エンジンであって、前記グリッドの部分を、論理的に関連したHPCノードの1つ又は複数の仮想クラスタに割り当てるよう動作可能であり、前記クラスタ管理エンジンは、前記ジョブに関連付けられたポリシー及びパラメータにより、前記ジョブを実行するために、特定の仮想クラスタを選択するよう動作可能であり、前記ジョブの次元により、前記ジョブの実行のために前記仮想クラスタのうちの選択された仮想クラスタ内にジョブ空間を割り当てるよう動作可能なクラスタ管理エンジンを更に備え、前記ジョブ空間は、別のジョブに関連付けられた別のジョブ空間とノードを共有するよう動作可能であることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、各HPCノード上の前記少なくとも2つのプロセッサが:
ホスト・チャネル・アダプタ(HCA)によって前記統合スイッチに結合されることを特徴とするHPCシステム。 - 請求項2記載のHPCシステムであって、各HPCノード上の前記少なくとも2つのプロセッサが:
ハイパ・トランスポート/PCIブリッジによって前記統合スイッチに更に結合されることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、各HPCノード上の前記少なくとも2つのプロセッサが:
ハイパ・トランスポート・リンクを介して通信可能に相互結合されることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、各HPCノード上の前記少なくとも2つのプロセッサが:
ノースブリッジによって前記統合スイッチに通信可能に結合されることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、各HPCノードの前記統合スイッチが:
前記少なくとも2つのプロセッサの帯域幅でI/Oメッセージを通信するよう動作可能であることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、各HPCノードの前記統合スイッチが:
インフィニバンド・スイッチ;
を備えることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって:
前記複数のHPCノードがトポロジに配置され;
前記トポロジが各HPCノードの統合ファブリックによって動作可能にされることを特徴とするHPCシステム。 - 請求項8記載のHPCシステムであって、前記トポロジが:
超立法体;
を備えることを特徴とするHPCシステム。 - 請求項8記載のHPCシステムであって、前記トポロジが:
畳んだトポロジ;
を備えることを特徴とするHPCシステム。 - 請求項1記載のHPCシステムであって、前記複数のHPCノードのうちの第1ノードが:
X軸に沿って前記複数のHPCノードのうちの第2ノードに相互接続され;
Y軸に沿って前記複数のHPCノードのうちの第3ノードに相互接続され;
Z軸に沿って前記複数のHPCノードのうちの第4ノードに相互接続され;かつ
対角軸に沿って第5ノードに相互接続されることを特徴とするHPCシステム。 - 請求項11記載のHPCシステムであって、前記第1ノードと前記第5ノードとの間の前記接続は、前記第2ノード、前記第3ノード、及び前記第4ノードのうちの何れかのジャンプがある場合、該ジャンプを削減することによって、前記複数のHPCノード間でのメッセージ・ジャンプを削減するよう動作可能であることを特徴とするHPCシステム。
- HPCジョブを実行する方法であって:
複数のHPCノードの少なくとも部分集合を、スイッチを介して相互接続する工程;
前記複数のHPCノードの各プロセッサを前記スイッチに結合する工程;
前記複数のHPCノードにおける前記プロセッサでHPCジョブを実行する工程;
前記複数のHPCノード、及び関連したプロセッサを相互接続するグリッドを提供する工程;
前記ジョブの前記実行において前記HPCノード、及び関連したプロセッサを動的に割り当て、管理する工程;
前記グリッドの一部分を、論理的に関連したHPCノードの1つ又は複数の仮想クラスタに割り当てる工程;
前記ジョブに関連付けられたポリシー及びパラメータにより、前記ジョブを実行するために、特定の仮想クラスタを選択する工程;及び
前記ジョブの次元により、前記ジョブの実行のために、前記仮想クラスタのうちの選択された仮想クラスタ内にジョブ空間を割り当てる工程とを備え、前記ジョブ空間は、別のジョブに関連付けられた別のジョブ空間とノードを共有するよう動作可能であることを特徴とする方法。 - 請求項13記載の方法であって、各プロセッサを前記スイッチに結合する工程が:
各プロセッサを前記スイッチにホスト・チャネル・アダプタ(HCA)を用いて結合する工程;
を備えることを特徴とする方法。 - 請求項14記載の方法であって、各プロセッサを前記スイッチに結合する工程が:
各プロセッサを前記スイッチにハイパ・トランスポート/PCIブリッジを用いて結合する工程;
を備えることを特徴とする方法。 - 請求項13記載の方法であって、
前記プロセッサを、ハイパ・トランスポート・リンクを介して結合する工程;
を更に備えることを特徴とする方法。 - 請求項13記載の方法であって、各プロセッサを前記スイッチに結合する工程が:
各プロセッサをノースブリッジを用いて前記スイッチに通信可能に結合する工程;
を備えることを特徴とする方法。 - 請求項13記載の方法であって、
前記プロセッサの帯域幅でI/Oメッセージを通信する工程を更に備えることを特徴とする方法。 - 請求項13記載の方法であって、前記スイッチが:
インフィニバンド・スイッチ;
を備えることを特徴とする方法。 - 請求項13記載の方法であって:
前記複数のHPCノードがトポロジに配置され;
前記トポロジが各HPCノードの統合ファブリックによって動作可能にされることを特徴とする方法。 - 請求項20記載の方法であって、前記トポロジが:
超立法体;
を備えることを特徴とする方法。 - 請求項20記載の方法であって、前記トポロジが:
畳んだトポロジ;
を備えることを特徴とする方法。 - 請求項13記載の方法であって、前記複数のHPCノードのうちの第1ノードが:
X軸に沿って前記複数のHPCノードのうちの第2ノードに相互接続され;
Y軸に沿って前記複数のHPCノードのうちの第3ノードに相互接続され;
Z軸に沿って前記複数のHPCノードのうちの第4ノードに相互接続され;かつ
対角軸に沿って第5ノードに相互接続されることを特徴とする方法。 - 請求項23記載の方法であって、前記第1ノードと前記第5ノードとの間の前記接続は、前記第2ノード、前記第3ノード、及び前記第4ノードのうちの何れかのジャンプがある場合、該ジャンプを削減することによって、前記複数のHPCノード間でのメッセージ・ジャンプを削減するよう動作可能であることを特徴とする方法。
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US10/824,874 US8335909B2 (en) | 2004-04-15 | 2004-04-15 | Coupling processors to each other for high performance computing (HPC) |
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JP4560435B2 true JP4560435B2 (ja) | 2010-10-13 |
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US (4) | US8335909B2 (ja) |
EP (2) | EP1566738A3 (ja) |
JP (1) | JP4560435B2 (ja) |
KR (1) | KR101159377B1 (ja) |
CN (1) | CN1704921B (ja) |
CA (1) | CA2503775C (ja) |
IL (1) | IL178608A (ja) |
MY (1) | MY147118A (ja) |
TW (1) | TWI338232B (ja) |
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MY147118A (en) | 2012-10-31 |
EP1814029A2 (en) | 2007-08-01 |
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US9037833B2 (en) | 2015-05-19 |
US20050235092A1 (en) | 2005-10-20 |
KR101159377B1 (ko) | 2012-06-27 |
US20150212964A1 (en) | 2015-07-30 |
CA2503775C (en) | 2012-08-28 |
US10289586B2 (en) | 2019-05-14 |
EP1566738A2 (en) | 2005-08-24 |
EP1566738A3 (en) | 2005-09-07 |
KR20070011503A (ko) | 2007-01-24 |
CA2503775A1 (en) | 2005-10-15 |
IL178608A0 (en) | 2007-02-11 |
CN1704921A (zh) | 2005-12-07 |
IL178608A (en) | 2012-07-31 |
US20130103929A1 (en) | 2013-04-25 |
JP2005316997A (ja) | 2005-11-10 |
TWI338232B (en) | 2011-03-01 |
WO2005106696A1 (en) | 2005-11-10 |
US8335909B2 (en) | 2012-12-18 |
TW200619972A (en) | 2006-06-16 |
CN1704921B (zh) | 2010-06-23 |
US10769088B2 (en) | 2020-09-08 |
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