JP4532846B2 - 半導体基板の製造方法 - Google Patents

半導体基板の製造方法 Download PDF

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Publication number
JP4532846B2
JP4532846B2 JP2003128917A JP2003128917A JP4532846B2 JP 4532846 B2 JP4532846 B2 JP 4532846B2 JP 2003128917 A JP2003128917 A JP 2003128917A JP 2003128917 A JP2003128917 A JP 2003128917A JP 4532846 B2 JP4532846 B2 JP 4532846B2
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JP
Japan
Prior art keywords
substrate
manufacturing
layer
semiconductor substrate
gallium arsenide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003128917A
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English (en)
Japanese (ja)
Other versions
JP2004335693A5 (ko
JP2004335693A (ja
Inventor
隆夫 米原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2003128917A priority Critical patent/JP4532846B2/ja
Priority to TW093111750A priority patent/TWI259514B/zh
Priority to KR1020057020457A priority patent/KR100725141B1/ko
Priority to CNA2007101812355A priority patent/CN101145509A/zh
Priority to PCT/JP2004/006178 priority patent/WO2004100233A1/en
Priority to EP04730068A priority patent/EP1620880A4/en
Priority to CNB2004800006869A priority patent/CN100358104C/zh
Publication of JP2004335693A publication Critical patent/JP2004335693A/ja
Priority to US11/039,285 priority patent/US20050124137A1/en
Publication of JP2004335693A5 publication Critical patent/JP2004335693A5/ja
Application granted granted Critical
Publication of JP4532846B2 publication Critical patent/JP4532846B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2003128917A 2003-05-07 2003-05-07 半導体基板の製造方法 Expired - Fee Related JP4532846B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2003128917A JP4532846B2 (ja) 2003-05-07 2003-05-07 半導体基板の製造方法
TW093111750A TWI259514B (en) 2003-05-07 2004-04-27 Semiconductor substrate and manufacturing method therefor
CNA2007101812355A CN101145509A (zh) 2003-05-07 2004-04-28 半导体衬底及其制造方法
PCT/JP2004/006178 WO2004100233A1 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor
KR1020057020457A KR100725141B1 (ko) 2003-05-07 2004-04-28 반도체 기판 및 그 제조방법
EP04730068A EP1620880A4 (en) 2003-05-07 2004-04-28 SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
CNB2004800006869A CN100358104C (zh) 2003-05-07 2004-04-28 半导体衬底及其制造方法
US11/039,285 US20050124137A1 (en) 2003-05-07 2005-01-19 Semiconductor substrate and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003128917A JP4532846B2 (ja) 2003-05-07 2003-05-07 半導体基板の製造方法

Publications (3)

Publication Number Publication Date
JP2004335693A JP2004335693A (ja) 2004-11-25
JP2004335693A5 JP2004335693A5 (ko) 2006-06-08
JP4532846B2 true JP4532846B2 (ja) 2010-08-25

Family

ID=33432059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003128917A Expired - Fee Related JP4532846B2 (ja) 2003-05-07 2003-05-07 半導体基板の製造方法

Country Status (6)

Country Link
EP (1) EP1620880A4 (ko)
JP (1) JP4532846B2 (ko)
KR (1) KR100725141B1 (ko)
CN (2) CN101145509A (ko)
TW (1) TWI259514B (ko)
WO (1) WO2004100233A1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5128781B2 (ja) * 2006-03-13 2013-01-23 信越化学工業株式会社 光電変換素子用基板の製造方法
CN108231695A (zh) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 复合衬底及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794409A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd Ｉｉｉ−ｖ族化合物半導体薄膜の形成方法
JP2000036583A (ja) * 1998-05-15 2000-02-02 Canon Inc 半導体基板、半導体薄膜の作製方法および多層構造体

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3879173B2 (ja) * 1996-03-25 2007-02-07 住友電気工業株式会社 化合物半導体気相成長方法
FR2784795B1 (fr) * 1998-10-16 2000-12-01 Commissariat Energie Atomique Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794409A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd Ｉｉｉ−ｖ族化合物半導体薄膜の形成方法
JP2000036583A (ja) * 1998-05-15 2000-02-02 Canon Inc 半導体基板、半導体薄膜の作製方法および多層構造体

Also Published As

Publication number Publication date
TW200425261A (en) 2004-11-16
WO2004100233A1 (en) 2004-11-18
KR20060005406A (ko) 2006-01-17
JP2004335693A (ja) 2004-11-25
EP1620880A1 (en) 2006-02-01
CN101145509A (zh) 2008-03-19
EP1620880A4 (en) 2008-08-06
CN1698180A (zh) 2005-11-16
KR100725141B1 (ko) 2007-06-07
TWI259514B (en) 2006-08-01
CN100358104C (zh) 2007-12-26

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