JP4532846B2 - Manufacturing method of semiconductor substrate - Google Patents

Manufacturing method of semiconductor substrate Download PDF

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Publication number
JP4532846B2
JP4532846B2 JP2003128917A JP2003128917A JP4532846B2 JP 4532846 B2 JP4532846 B2 JP 4532846B2 JP 2003128917 A JP2003128917 A JP 2003128917A JP 2003128917 A JP2003128917 A JP 2003128917A JP 4532846 B2 JP4532846 B2 JP 4532846B2
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JP
Japan
Prior art keywords
substrate
manufacturing
layer
semiconductor substrate
gallium arsenide
Prior art date
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Expired - Fee Related
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JP2003128917A
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Japanese (ja)
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JP2004335693A5 (en
JP2004335693A (en
Inventor
隆夫 米原
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2003128917A priority Critical patent/JP4532846B2/en
Priority to TW093111750A priority patent/TWI259514B/en
Priority to PCT/JP2004/006178 priority patent/WO2004100233A1/en
Priority to KR1020057020457A priority patent/KR100725141B1/en
Priority to EP04730068A priority patent/EP1620880A4/en
Priority to CNB2004800006869A priority patent/CN100358104C/en
Priority to CNA2007101812355A priority patent/CN101145509A/en
Publication of JP2004335693A publication Critical patent/JP2004335693A/en
Priority to US11/039,285 priority patent/US20050124137A1/en
Publication of JP2004335693A5 publication Critical patent/JP2004335693A5/ja
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Publication of JP4532846B2 publication Critical patent/JP4532846B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体基板及びその製造方法に係り、特にガリウム砒素層を有する半導体基板及びその製造方法に関する。
【０００２】
【従来の技術】
ガリウム砒素等からなる化合物半導体基板上のデバイスはシリコンでは得られない高い性能、たとえば、優れた高速性、発光性などを持っている。しかしながら、化合物半導体基板は、高価で、機械的強度が低く、大面積基板の作製が容易ではない等の問題点がある。
【０００３】
このようなことから、安価で、機械的強度も高く、大面積基板を得られるシリコン基板上に、化合物半導体をヘテロエピタキシャル成長させる等の試みがなされている。例えば、特許第３２５７６２４号公報には、シリコン基板上に化合物半導体層をヘテロエピタキシャル成長させた後にイオン注入を行い、このシリコン基板を別の基板と結合し、次いで、加熱によりイオン注入層を崩壊させて結合基板を分割することにより、大面積の化合物半導体基板を得る方法が開示されている。このような方法の場合、求められる化合物半導体基板の仕様によっては、シリコンと化合物半導体との間に存在する格子定数の不整合を緩和させて、良好な結晶性を得る必要がある。
【０００４】
特許第２８７７８００号公報には、シリコン基板に形成した多孔質シリコン層上に化合物半導体層を成長させた後、このシリコン基板を別の基板と結合し、次いで、流体の噴流により多孔質シリコン層を破断させて結合基板を分割することによって、化合物半導体基板を得る方法が開示されている。
【０００５】
【特許文献１】
特許第３２５７６２４号公報
【特許文献２】
特許第２８７７８００号公報
【０００６】
【発明が解決しようとする課題】
特許第２８７７８００号公報に開示された製造方法では、シリコンと化合物半導体との間に多孔質シリコン層を介在させることで、シリコンと化合物半導体との格子定数の不整合をある程度緩和して、ヘテロエピタキシャル層を形成している。しかしながら、多孔質シリコンと化合物半導体との格子定数の不整合を無くすことは容易ではないので、得られた化合物半導体の結晶性に問題を残すこともある。そして、求められる化合物半導体デバイスの仕様によっては、このような製造方法による化合物半導体基板を適用し得る範囲が限定されてしまい、化合物半導体デバイスの優位性を生かしきれないこともある。
【０００７】
本発明は、上記の考察を基礎としてなされたものであり、化合物半導体デバイスの優位性を十分に発揮し、且つ経済性を確保し得る半導体基板の製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明に係る半導体基板の製造方法は、ゲルマニウム基板と前記ゲルマニウム基板上に配されたガリウム砒素層と前記ゲルマニウム基板あるいは前記ガリウム砒素層の少なくともいずれか一方に形成されたイオン注入層とを有する第１基板を作製する工程と、前記第１基板と第２基板とを結合させて結合基板を作製する工程と、前記結合基板を前記イオン注入層の部分で分割する工程と、を含むことを特徴とする。
【０００９】
本発明の好適な実施の形態によれば、前記第１基板の作製工程は、エピタキシャル成長法により前記ガリウム砒素層を形成する工程を含むことが好ましい。さらに、前記ガリウム砒素層の上に化合物半導体層を形成する工程を含んでもよい。
【００１０】
本発明の好適な実施の形態によれば、前記イオンは、水素ガス又は希ガスイオンからなることが好ましい。
【００１１】
本発明の好適な実施の形態によれば、前記分割工程は、前記結合基板に熱処理を施すことにより前記イオン注入層の部分を分割する工程を含むことが好ましい。
【００１２】
本発明の好適な実施の形態によれば、前記分割工程は、流体の噴流または静圧により前記イオン注入層の部分を分割する工程を含むことが好ましい。
【００１３】
本発明の好適な実施の形態によれば、前記分割工程は、部材を前記イオン注入層に挿入することにより前記イオン注入層の部分を分割する工程を含むことが好ましい。
【００１４】
本発明の好適な実施の形態によれば、前記分割工程の後に、第２基板上の前記ガリウム砒素層の上に残留する前記ゲルマニウム層の部分を除去する工程を含むことが好ましい。
【００１５】
本発明の好適な実施の形態によれば、前記分割工程の後に、第１基板の表面を平坦化して前記第１基板の作製工程に再利用する工程を含むことが好ましい。
【００１６】
【発明の実施の形態】
以下、添付図面を参照しながら本発明の好適な実施の形態を説明する。
【００１７】
図１〜図７は、本発明の好適な実施の形態に係る基板の製造方法を説明するための図である。図１に示す工程では、ゲルマニウム基板１１を準備する。次いで、図２に示す工程では、ゲルマニウム基板１１の表面上にエピタキシャル成長法によりガリウム砒素層１２を形成する。ゲルマニウムとガリウム砒素との格子定数の不整合は微小であるため、結晶性の良好なガリウム砒素層をゲルマニウム基板上に形成することができる。また、エピタキシャル成長法によれば、厚さが均一なガリウム砒素層を形成することができる。
【００１８】
図３に示す工程では、図２に示すガリウム砒素層１２の表面から水素イオンを注入して、ガリウム砒素層１２の内部にイオン注入層１３を形成して、第１基板１０を形成する。注入に使用されるイオンは水素のほか、ヘリウム、ネオン、アルゴン、クリプトン及びキセノンのような希ガスのイオンを単独でもしくは組み合わせて使用し得る。なお不図示ながら、イオン注入に先立って、ガリウム砒素層１２の表面に絶縁層を形成している。イオン注入層１３を形成する領域はゲルマニウム基板１１あるいはガリウム砒素層１２の少なくともいずれか一方に形成することで実施し得る。
【００１９】
図４に示す工程では、図３に示す第１基板１０の表面に第２基板２０を結合させて、結合基板３０を形成する。第２基板２０としては、典型的には、シリコン基板又はその表面にＳｉＯ２層等の絶縁層を形成した基板を採用することができる。また、第２基板２０は、それ以外の基板、例えばガラス基板等の絶縁性基板であってもよい。
【００２０】
図５に示す工程では、結合基板３０をイオン注入層１３の部分で破断することにより２枚の基板に分割する。イオン注入層１３は、微小な空洞（ｍｉｃｒｏ−ｃａｖｉｔｙ）、気泡（ｍｉｃｒｏ−ｂｕｂｂｌｅ）、歪或いは欠陥が集中的に生じたような構造を有し、結合基板３０のほかの部分に比べて脆弱である。この分割は、例えば、結合基板３０に熱処理を施すことによって実施することができる。さらに、例えば、流体を使って行うことができる。流体を使う方法としては、例えば、流体（液体又は気体）の噴流を形成してこれを分離層１２に打ち込む方法や、流体の静圧を利用する方法等が好適である。前者の方法においては、流体として水を利用する方法は、ウォータージェット法と呼ばれる。さらに、上記の分割は、例えば、固体の楔等の部材を分離層１２に挿入することによっても実施することができる。
【００２１】
図６に示す工程では、第２基板２０のガリウム砒素層１２ｂ上に残留しているイオン注入層１３ｂをエッチング液等を使って除去する。このとき、ガリウム砒素層１２ｂをエッチングストップ層として利用すればよい。この後、必要に応じて、水素アニール工程、研磨工程等の平坦化工程を実施して平坦化してもよい。
【００２２】
以上の方法により、図７に示すような半導体基板４０が得られる。図７に示す半導体基板４０は、表面に薄いガリウム砒素層１２ｂを有する。ここで、薄いガリウム砒素層とは、一般的は半導体基板に比べて薄いことを意図した表現であり、ガリウム砒素層１２ｂの厚さは、半導体デバイスの優位性を発揮する上で、例えば、５ｎｍ〜５μｍの範囲が好ましい。さらには、半導体デバイスの仕様によっては、ガリウム砒素層１２ｂの上に、ＡｌＧａＡｓ、ＧａＰ、ＩｎＰ、ＩｎＡｓ等の他の化合物半導体層を形成することもできる。
【００２３】
また、図５に示す工程によって分割した後、ゲルマニウム基板１１上に残留している分離層１３ａ等をエッチング液等を使って除去する。また、水素アニール、研磨工程等を実施して、ゲルマニウム基板の表面を平坦化し、図１に示す工程で使用するゲルマニウム基板１１として再使用することもできる。このようにゲルマニウム基板１１を繰り返して使用することにより、半導体基板の製造コストを大幅に低減させることができる。
【００２４】
以上のように、本発明に係る製造方法によれば、膜厚が均一で且つ結晶性の良好なガリウム砒素層を有する半導体基板を得ることができる。また、本発明に係る製造方法によれば、ガリウム砒素層を有する半導体基板の製造コストを大幅に低減させることができる。
【００２５】
【発明の効果】
本発明によれば、化合物半導体デバイスの優位性を十分に発揮し、且つ経済性を確保し得る半導体基板の製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図２】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図３】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図４】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図５】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図６】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【図７】本発明の好適な実施の形態に係る半導体基板の製造方法を説明するための図である。
【符号の説明】
１０ 第１基板
１１ ゲルマニウム基板
１２、１２ａ、１２ｂ ガリウム砒素層
１３ イオン注入層
２０ 第２基板
３０ 結合基板
４０ ガリウム砒素基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a manufacturing method thereof, and more particularly to a semiconductor substrate having a gallium arsenide layer and a manufacturing method thereof.
[0002]
[Prior art]
A device on a compound semiconductor substrate made of gallium arsenide or the like has high performance that cannot be obtained by silicon, such as excellent high-speed performance and light emission. However, the compound semiconductor substrate has problems such as high cost, low mechanical strength, and difficulty in manufacturing a large area substrate.
[0003]
For this reason, attempts have been made to heteroepitaxially grow a compound semiconductor on a silicon substrate that is inexpensive, has high mechanical strength, and can obtain a large-area substrate. For example, in Japanese Patent No. 3257624, a compound semiconductor layer is heteroepitaxially grown on a silicon substrate, ion implantation is performed, the silicon substrate is bonded to another substrate, and then the ion implantation layer is collapsed by heating. A method of obtaining a compound semiconductor substrate with a large area by dividing a bonded substrate is disclosed. In the case of such a method, depending on the required specification of the compound semiconductor substrate, it is necessary to relax the mismatch of the lattice constant existing between silicon and the compound semiconductor to obtain good crystallinity.
[0004]
In Japanese Patent No. 2877800, after a compound semiconductor layer is grown on a porous silicon layer formed on a silicon substrate, this silicon substrate is bonded to another substrate, and then the porous silicon layer is formed by a jet of fluid. A method for obtaining a compound semiconductor substrate by breaking and separating a bonded substrate is disclosed.
[0005]
[Patent Document 1]
Japanese Patent No. 3257624 [Patent Document 2]
Japanese Patent No. 2877800 [0006]
[Problems to be solved by the invention]
In the manufacturing method disclosed in Japanese Patent No. 2877800, a porous silicon layer is interposed between silicon and a compound semiconductor, so that the mismatch of lattice constant between silicon and the compound semiconductor is alleviated to some extent, and heteroepitaxial. Forming a layer. However, since it is not easy to eliminate the lattice constant mismatch between the porous silicon and the compound semiconductor, a problem may remain in the crystallinity of the obtained compound semiconductor. Depending on the required specifications of the compound semiconductor device, the range in which the compound semiconductor substrate by such a manufacturing method can be applied is limited, and the superiority of the compound semiconductor device may not be fully utilized.
[0007]
The present invention has been made on the basis of the above considerations, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate that can sufficiently exhibit the superiority of a compound semiconductor device and can ensure economic efficiency.
[0008]
[Means for Solving the Problems]
A method of manufacturing a semiconductor substrate according to the present invention includes a germanium substrate, a gallium arsenide layer disposed on the germanium substrate, and an ion implantation layer formed on at least one of the germanium substrate or the gallium arsenide layer. Including a step of manufacturing one substrate, a step of combining the first substrate and the second substrate to manufacture a combined substrate, and a step of dividing the combined substrate at a portion of the ion implantation layer. And
[0009]
According to a preferred embodiment of the present invention, it is preferable that the step of manufacturing the first substrate includes a step of forming the gallium arsenide layer by an epitaxial growth method. Furthermore, a step of forming a compound semiconductor layer on the gallium arsenide layer may be included.
[0010]
According to a preferred embodiment of the present invention, the ions are preferably composed of hydrogen gas or rare gas ions.
[0011]
According to a preferred embodiment of the present invention, the dividing step preferably includes a step of dividing the portion of the ion implantation layer by performing a heat treatment on the combined substrate.
[0012]
According to a preferred embodiment of the present invention, the dividing step preferably includes a step of dividing a portion of the ion implantation layer by a fluid jet or a static pressure.
[0013]
According to a preferred embodiment of the present invention, the dividing step preferably includes a step of dividing a portion of the ion implantation layer by inserting a member into the ion implantation layer.
[0014]
According to a preferred embodiment of the present invention, it is preferable that after the dividing step, a step of removing a portion of the germanium layer remaining on the gallium arsenide layer on the second substrate is included.
[0015]
According to a preferred embodiment of the present invention, it is preferable that after the dividing step, a step of flattening a surface of the first substrate and reusing it in the manufacturing step of the first substrate is included.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
[0017]
FIGS. 1-7 is a figure for demonstrating the manufacturing method of the board | substrate which concerns on suitable embodiment of this invention. In the process shown in FIG. 1, a germanium substrate 11 is prepared. Next, in the process shown in FIG. 2, a gallium arsenide layer 12 is formed on the surface of the germanium substrate 11 by epitaxial growth. Since the mismatch in lattice constant between germanium and gallium arsenide is very small, a gallium arsenide layer with good crystallinity can be formed on the germanium substrate. Moreover, according to the epitaxial growth method, a gallium arsenide layer having a uniform thickness can be formed.
[0018]
In the step shown in FIG. 3, hydrogen ions are implanted from the surface of the gallium arsenide layer 12 shown in FIG. 2, and the ion implantation layer 13 is formed inside the gallium arsenide layer 12 to form the first substrate 10. As ions used for implantation, ions of rare gases such as helium, neon, argon, krypton and xenon can be used alone or in combination, in addition to hydrogen. Although not shown, an insulating layer is formed on the surface of the gallium arsenide layer 12 prior to ion implantation. The region for forming the ion implantation layer 13 can be implemented by forming it in at least one of the germanium substrate 11 and the gallium arsenide layer 12.
[0019]
In the step shown in FIG. 4, the second substrate 20 is bonded to the surface of the first substrate 10 shown in FIG. As the second substrate 20, typically, a silicon substrate or a substrate on which an insulating layer such as a SiO 2 layer is formed can be employed. The second substrate 20 may be another substrate, for example, an insulating substrate such as a glass substrate.
[0020]
In the process shown in FIG. 5, the bonded substrate 30 is divided into two substrates by breaking at the portion of the ion implantation layer 13. The ion-implanted layer 13 has a structure in which micro-cavities, micro-bubbles, strains or defects are concentrated, and is weaker than other parts of the bonding substrate 30. is there. This division can be performed, for example, by subjecting the bonded substrate 30 to a heat treatment. Further, for example, it can be performed using a fluid. As a method of using the fluid, for example, a method of forming a jet of fluid (liquid or gas) and driving it into the separation layer 12 or a method of using the static pressure of the fluid is suitable. In the former method, a method of using water as a fluid is called a water jet method. Furthermore, the above-described division can also be performed by inserting a member such as a solid wedge into the separation layer 12, for example.
[0021]
In the step shown in FIG. 6, the ion implantation layer 13b remaining on the gallium arsenide layer 12b of the second substrate 20 is removed using an etching solution or the like. At this time, the gallium arsenide layer 12b may be used as an etching stop layer. Thereafter, planarization may be performed by performing a planarization process such as a hydrogen annealing process and a polishing process, if necessary.
[0022]
With the above method, a semiconductor substrate 40 as shown in FIG. 7 is obtained. The semiconductor substrate 40 shown in FIG. 7 has a thin gallium arsenide layer 12b on the surface. Here, the thin gallium arsenide layer is an expression intended to be generally thinner than the semiconductor substrate, and the thickness of the gallium arsenide layer 12b is, for example, 5 nm in order to exhibit the superiority of the semiconductor device. A range of ˜5 μm is preferred. Furthermore, other compound semiconductor layers such as AlGaAs, GaP, InP, and InAs may be formed on the gallium arsenide layer 12b depending on the specifications of the semiconductor device.
[0023]
Further, after the division by the process shown in FIG. 5, the separation layer 13a and the like remaining on the germanium substrate 11 are removed using an etching solution or the like. Further, the surface of the germanium substrate can be flattened by performing hydrogen annealing, a polishing step, and the like, and can be reused as the germanium substrate 11 used in the step shown in FIG. Thus, by repeatedly using the germanium substrate 11, the manufacturing cost of the semiconductor substrate can be greatly reduced.
[0024]
As described above, according to the manufacturing method of the present invention, a semiconductor substrate having a gallium arsenide layer with a uniform film thickness and good crystallinity can be obtained. In addition, according to the manufacturing method of the present invention, the manufacturing cost of a semiconductor substrate having a gallium arsenide layer can be greatly reduced.
[0025]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor substrate which can fully exhibit the predominance of a compound semiconductor device and can ensure economical efficiency can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 3 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 4 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 5 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 6 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 7 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.
[Explanation of symbols]
10 First substrate 11 Germanium substrates 12, 12a, 12b Gallium arsenide layer 13 Ion implantation layer 20 Second substrate 30 Bonded substrate 40 Gallium arsenide substrate

Claims (7)

ガリウム砒素層を有する半導体基板の製造方法であって、ゲルマニウム基板と前記ゲルマニウム基板上に配されたガリウム砒素層と前記ゲルマニウム基板あるいは前記ガリウム砒素層の少なくともいずれか一方に形成されたイオン注入層とを有する第１基板を製作する工程と、前記第１基板と第２基板とを結合させて結合基板を作製する工程と、前記結合基板を前記イオン注入層の部分で分割する工程と、を含むことを特徴とする半導体基板の製造方法。  A method for manufacturing a semiconductor substrate having a gallium arsenide layer, comprising: a germanium substrate; a gallium arsenide layer disposed on the germanium substrate; and an ion implantation layer formed on at least one of the germanium substrate or the gallium arsenide layer; Manufacturing a first substrate having the following steps: bonding the first substrate and the second substrate to form a combined substrate; and dividing the combined substrate at a portion of the ion implantation layer. A method of manufacturing a semiconductor substrate. 前記第１基板の作製工程は、エピタキシャル成長法により前記ガリウム砒素層を形成する工程を含む請求項１に記載の半導体基板の製造方法。  2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the manufacturing step of the first substrate includes a step of forming the gallium arsenide layer by an epitaxial growth method. 前記第１基板の作製工程は、前記ガリウム砒素層の上に化合物半導体層を形成する工程を含む請求項１に記載の半導体基板の製造方法。  2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the manufacturing step of the first substrate includes a step of forming a compound semiconductor layer on the gallium arsenide layer. 前記イオンは、水素ガスイオン又は希ガスイオンからなる請求項１に記載の半導体基板の製造方法。  The method of manufacturing a semiconductor substrate according to claim 1, wherein the ions are hydrogen gas ions or rare gas ions. 前記分割工程は、前記結合基板に熱処理を施すことにより前記イオン注入層の部分を分割する工程を含む請求項１に記載の半導体基板の製造方法。  The method of manufacturing a semiconductor substrate according to claim 1, wherein the dividing step includes a step of dividing the portion of the ion implantation layer by performing a heat treatment on the combined substrate. 前記分割工程は、流体の噴流または静圧により前記イオン注入層の部分を分割する工程を含む請求項１に記載の半導体基板の製造方法。  The method of manufacturing a semiconductor substrate according to claim 1, wherein the dividing step includes a step of dividing a portion of the ion implantation layer by a jet of fluid or a static pressure. 前記分割工程は、部材を前記イオン注入層に挿入することにより前記イオン注入層の部分を分割する工程を含む請求項１に記載の半導体基板の製造方法。  The method of manufacturing a semiconductor substrate according to claim 1, wherein the dividing step includes a step of dividing a portion of the ion implantation layer by inserting a member into the ion implantation layer.
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* Cited by examiner, † Cited by third party
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