JP2000349267A - Method of fabricating semiconductor member - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen a semiconductor member in manufacturing cost by a method wherein an epitaxial growth layer is formed on the one surface of a substrate specific times as thick as the porous semiconductor layer before a porous semiconductor layer is formed, and a porous semiconductor layer is formed on a separated epitaxial growth layer. SOLUTION: An epitaxial growth layer 12 is formed on the one surface of a first substrate 11. Then, the surface layer of the epitaxial growth layer 12 is turned porous, and a porous semiconductor layer 13 is formed. At this point, the thickness tps of the porous semiconductor layer 13 is set half or below as thick as the thickness te of the epitaxial growth layer 12. Then, a non-porous single crystal semiconductor layer 14 such as a non-porous single crystal silicon layer is formed on the porous semiconductor layer 13. The first substrate 11 and the second substrate 16 are joined together through the intermediary of insulating layers 15 and 17 at a room temperature and then pasted together through anodic bonding, pressurization, or a thermal treatment. The pasted substrates are separated at an interface located in the porous semiconductor layer 3 or either above or below it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor member.

[0002]

2. Description of the Related Art A single crystal semiconductor layer is formed on an insulator by using a silicon-on-insulator or a semiconductor-on-insulator (hereinafter, referred to as SOI).
A great deal of research has been conducted on devices using SOI technology, which are widely known as technologies and cannot be attained with a bulk silicon substrate for manufacturing a normal silicon integrated circuit, because they have many advantages. That is, using the SOI technology has the following advantages. That is, (1) high integration can be easily achieved by dielectric isolation. (2) Excellent resistance to radiation. (3) The stray capacitance is reduced and the speed can be increased. (4) The well step can be omitted. (5) Latch-up can be prevented. (6) A fully depleted field effect transistor by thinning is possible. And other advantages.

[0003] Among the methods for manufacturing an SOI wafer, a method of forming a non-single-crystal semiconductor layer on a porous layer as disclosed in the specification of US Pat. No. 5,371,037 and transferring it to a supporting substrate via an insulating layer. Is that the thickness of the SOI layer is excellent in uniformity, the density of crystal defects in the SOI layer is easily controlled, the surface flatness of the SOI layer is good, and expensive special specification equipment is not required for manufacturing. That, number 10n
This is very excellent in that it can be manufactured with the same apparatus in the SOI film thickness range from about m to about 10 μm.

[0004] In addition, US Pat.
6,229, that is, forming a non-porous single-crystal semiconductor layer on the porous layer of the first substrate having a porous layer, After bonding the second substrate to the first substrate,
By separating the first substrate and the second substrate without destroying them, smoothing the surface of the first substrate, forming porous again, and reusing the first substrate, the first substrate can be repeated many times. Can be used.

[0005] Therefore, there is a great effect that the manufacturing cost can be greatly reduced and the manufacturing process itself can be simplified. Such first
As a method for separating a bonded substrate that separates both the substrate and the second substrate without breaking, the following methods are available.

For example, a method of pulling in the direction perpendicular to the bonding surface, a method of applying a shearing stress in parallel to the bonding surface (for example, moving the respective substrates in directions parallel to the bonding surface in opposite directions) And a method of rotating each substrate in the opposite direction in the circumferential direction), a method of applying pressure in a direction perpendicular to the bonding surface, and a method of applying wave energy such as ultrasonic waves to the separation region.

Further, a method of inserting a peeling member (for example, a sharp blade such as a knife) into the separation region from the side surface of the bonded substrate in parallel with the bonding surface, soaks the porous layer functioning as the separation region. Method of utilizing the expansion energy of the material that has been used, a method of thermally oxidizing and expanding the volume from the side of the porous layer-bonded substrate that functions as a separation region, and a method of bonding the porous layer that functions as a separation region to the side of the bonded substrate. Selective etching and separation method,
There is a method in which a layer capable of obtaining microcavities formed by ion implantation as a separation region is separated by heating by laser irradiation or the like.

In the prior art, a porous layer is formed on the surface of a first substrate, a non-porous semiconductor single crystal film is formed on the porous layer, and the film is bonded to a second substrate. In the method of manufacturing a semiconductor member by removing and transferring the non-porous semiconductor single crystal film on a second substrate, the structure of the porous layer formed on the surface of the first substrate is It is closely related to the number of stacking faults introduced into the non-porous semiconductor single crystal film formed thereon, and it is necessary to control the specific resistance of the first substrate in order to control the structure of the porous layer. is there.

Generally, stacking faults are said to increase the leakage current at the pn junction when metal impurities are deposited at dislocations surrounding the stacking faults, thereby degrading the minority carrier lifetime. Further, there is a concern that the metal deposition causes deterioration of the dielectric strength of the oxide film. Therefore, it is important to reduce the stacking fault density when putting the SOI wafer into practical use. In particular, in a bipolar transistor, an increase in the leakage current of the pn junction is fatal.

However, a normally available CZ substrate has a specific resistance of 0.01 to 0.02 Ωcm and ± 5 even in an ingot.
A variation of as much as 0% is observed. Such a variation in specific resistance makes it difficult to control the porous structure. The porous structure has a high stacking fault density introduced into the non-porous semiconductor single crystal film formed on the porous layer and a high porosity used for separation. It greatly affects the structure control of the layer. That is, it is important to stably control the specific resistance in fabricating an SOI wafer, but it is difficult as long as a CZ substrate is used.

As a method for overcoming this, for example, as disclosed by Sakaguchi et al. In Japanese Patent Application Laid-Open No. 9-102594, a diffusion region is formed by diffusing an element capable of controlling the conductivity type in a silicon substrate. There is a way. However, in this method, the thickness of the diffusion region is controlled mainly by controlling the temperature and time of the heat treatment, so that the resistivity is uniform within the substrate surface and the resistivity is also uniform in the depth direction from the substrate surface. Distribution occurs. Further, since the CZ substrate is used, the problems of swirl and COP described below remain.

A swirl or COP exists in a CZ substrate generally used. When a substrate having a COP is used for manufacturing an SOI wafer, when this COP is present in the SOI layer, a defect called an HF defect is formed. Since silicon does not exist in the HF defect, SOI
It becomes a fatal defect as a substrate.

In addition, if swirl occurs due to uneven concentration of impurities in the surface of the substrate, the porous structure causes uneven distribution of the thickness of the porous layer when the porous layer is formed. Further, if a boron doped layer of, for example, 10 ¹⁸ / cm ³ is to be formed with a thickness of 10 μm by the diffusion method, the concentration is 10 ¹⁹ / cm ³ to 10 ²⁰ / c near the surface at the initial stage of the diffusion.
m ³ , making it easier to introduce defects.

Therefore, as a method of controlling the specific resistance of the first substrate, there is a method of using epitaxial silicon in a region where a porous layer is formed. Porous silicon is formed in the epitaxial silicon layer, and SO 3 is formed through subsequent steps.
When I was manufactured, epitaxial silicon had to be formed again on the first substrate, so that it was necessary to go through the epitaxial silicon forming step the same number of times as forming the SOI wafer. The process of growing epitaxial silicon involves many steps and takes time, which is a problem in terms of manufacturing cost. This point will be described in detail.

FIG. 6 is a schematic view for explaining a conventional method for manufacturing a semiconductor member. As shown in FIG. 6A, a first base 11 such as silicon is prepared. As shown in FIG. 6B, an epitaxial growth layer 12 is formed on the surface of the first base 11. As shown in FIG. 6C, the porous layer 13 is formed by making the epitaxial growth layer 12 porous by anodizing or the like.

As shown in FIG. 6D, the porous layer 13
A non-porous semiconductor layer 14 is epitaxially grown on the surface of the substrate. As shown in FIG. 6E, an insulating layer 15 is formed on the surface of the semiconductor layer 14 as necessary. As shown in FIG. 6 (f), a second substrate 16 such as silicon
Prepare If necessary, an insulating layer 17 may be formed on the second base 16.
Formed on the surface of

As shown in FIG. 6 (g), the first and second
Are bonded together. As shown in FIG. 6H, when a separating force is externally applied to the first and second bases 11 and 16, cracks occur in the porous layer having relatively low mechanical strength, and the first and second bases 11 and 16 are cracked. The second substrate is separated. On the separated surface of the separated first substrate 11, a residual porous body 13B is formed, and on the separated surface of the separated second substrate 16 (actually, on the surface of the semiconductor layer 14). Body 1
3A remains.

As shown in FIG. 6I, the residual porous body is removed by etching or the like. As shown in FIG. 6 (j), the surface having the surface roughness caused by the etching is smoothed by hydrogen annealing, polishing or the like. The residual porous body 13A on the second base 16 is also removed by etching or the like, and the surface is smoothed by hydrogen annealing. Thus,
A semiconductor member having an SOI structure as shown in FIG.

When another semiconductor member having the SOI structure is to be formed, the first base member 11 obtained in the step of FIG.
6B, an epitaxial growth layer 12 is formed again in the same manner as in the step of FIG.
What is necessary is just to flow to the process of (l).

[0020]

Here, the epitaxial growth step shown in FIG.
Is always performed as a pre-processing step every time is formed. Therefore, this epitaxial growth step has increased the manufacturing cost in manufacturing a semiconductor member.

Therefore, an object of the present invention is to manufacture a semiconductor member at low cost.

[0022]

In order to solve the above-mentioned problems, the present invention comprises a step of forming a porous semiconductor layer on at least one surface of a first substrate, and a step of forming a non-porous layer on the porous semiconductor layer. A step of forming a single-crystal semiconductor layer, a step of bonding the non-porous single-crystal semiconductor layer of the first base to a second base, and a step of bonding the base formed by bonding to the porous semiconductor layer. And a method of manufacturing a semiconductor member having at least a step of forming a porous semiconductor layer on the one surface of the first base before the step of forming the porous semiconductor layer. Forming at least n times (n ≧ 2) thickness;
Forming a porous semiconductor layer on the epitaxially grown layer after the separation.

Further, the method of manufacturing a semiconductor member according to the present invention comprises:
Forming an epitaxially grown layer having a thickness of te on the surface of the first base; and forming a porous layer having a thickness of tps not exceeding half the thickness of te on the surface of the epitaxially grown layer. Forming a non-porous layer on the porous layer, separating the non-porous layer from the first substrate, and forming a porous layer on the surface of the separated epitaxially grown layer And

Further, in the method of manufacturing a semiconductor member according to the present invention, after the step of separating the non-porous layer from the first substrate, a step of smoothing the surface of the residual epitaxial growth layer; Forming a porous layer on the surface of an epitaxial growth layer, forming a non-porous layer on the porous layer, and separating the non-porous layer from the first substrate. Good to do.

That is, according to the present invention, at least a second round of the porous layer is formed in order to epitaxially grow the consumed portion of the epitaxially grown layer in the porous layer forming step in the second and subsequent rounds to a thickness that is considered in advance. There is no need to perform epitaxial growth again immediately before forming the layer.

[0026]

(Embodiment 1) FIG. 1 is a manufacturing process diagram of a semiconductor member of this embodiment. The manufacturing process of the semiconductor member of the present embodiment will be described with reference to FIG. As shown in FIG. 1A, first, a first base 11 made of a silicon single crystal base or the like is prepared.

As the first base, a P-type or N-type semiconductor substrate is preferably used. Specifically, the first base is made of a single crystal substrate of an elemental semiconductor such as a Si wafer or SiG.
A single crystal substrate of a compound semiconductor such as e, SiC, or GaAs is used. Since the first substrate is subjected to epitaxial growth, the specific resistance is, for example, 0.01 Ω · cm to 100 Ω ·
Use a material with a wide allowable range of cm. Therefore, not only high-quality wafers but also low-quality wafers generally available as dummy grades can be used.

Next, an epitaxial growth layer 12 is formed on at least one surface of the first base 11.
(B)). The thickness te of the epitaxial growth layer 12
Is, as described later, at least twice, more preferably at least three times, the layer thickness tps of the porous layer.

In epitaxial growth, the specific resistance can be very strictly controlled by controlling impurities during crystal growth, which is a very effective means for controlling the porous structure. Furthermore, since the structure of the porous layer is controlled by the specific resistance of the epitaxial growth layer formed on the surface of the first substrate, it is not necessary to select the type of the first base on which the epitaxial growth layer is formed.

The method of forming the epitaxial growth layer 12 formed on the surface of the first substrate 11 may be any method as long as it does not easily cause crystal defects. , A thermal CVD method, a photo CVD method, a bias sputtering method, a liquid phase growth method, or the like.

The epitaxial growth layer may be any layer that can be made porous by anodization, ion implantation of hydrogen or an inert gas, or the like. Si, Ge, C, SiGe, Si
It can be formed from a semiconductor layer such as C, GaAs, GaAl, InP, and GaN.

The specific resistance of the epitaxial growth layer 12 is not particularly limited as long as it is suitable for forming a porous layer, but it is preferable that the in-plane distribution of the specific resistance is narrower than ± 10% to ± 5%. In addition, it is sufficient that the thickness of the epitaxial growth layer 12 is smaller than ± 10% to ± 3%.

The separation region refers to a region that collapses or cracks in a subsequent separation step. The main example is that the separation region is formed in a layer parallel to the surface at a portion deeper than the surface and can be separated without breaking the surface and its vicinity.

In the present embodiment, the separation region is preferably formed in the epitaxial growth layer formed on the first substrate, and is located at a position different from the bonding interface (bonding surface) with the second substrate. In the separation step, it is necessary not to separate from the bonding interface but to separate in a separation region at a position different from the bonding interface.

Therefore, it is preferable that the mechanical strength of the separation region is weaker than the mechanical strength of the bonding interface, and the separation region is broken before the bonding interface in the separation step. As a result, when the separation layer is broken, a portion having a specific thickness on the surface side of the first substrate is separated from the first substrate while being adhered to the second substrate, and is transferred onto the second substrate. . As a typical example of the separation region, a porous layer having at least one of an independent hole and a communication hole may be used.

Then, the surface layer of the epitaxial growth layer 12 is made porous (FIG. 1C) to form a porous semiconductor layer 13 made of a porous silicon layer or the like. At this time, the layer thickness tps of the porous layer 13 is equal to the layer thickness t of the epitaxial growth layer.
It is better not to exceed half of e.

The porosity of the porous layer suitable for separation is generally in the range of 10 to 80%, more preferably 20 to 6%.
The range is 0%. The porous layer can be formed by an anodizing method, an ion implantation method, or the like. The porous layer may be a single layer having a single porosity, but in order to facilitate mechanical separation and to stably show cracking positions, a plurality of porous layers are used. It may be formed by the body.

Such a porous body may be composed of two layers or three or more layers. The porous body may have an intermittent porosity change at the interface between the layers, or may have a continuous porosity. May change.

As the porous layer 13 located on the side of the epitaxial growth layer 12, a layer having a relatively low porosity, in other words, a low porosity layer in which the proportion of holes (bubbles or cavities) is low is preferably used. Its porosity is for example 30%
Desirably less than. Suitable thickness of the low porosity layer is, for example, 0.1 μm to 100 μm.

As the porous layer located at a position distant from the epitaxial growth layer 12, a layer with high porosity is preferable, and it is particularly preferable that the porosity is, for example, 30% or more. Such a high porosity layer has relatively low mechanical strength, and tends to be concentrated at the interface thereof. As a result, cracks and collapses occur preferentially inside the layer or at the upper and lower interfaces. A preferred upper limit for the thickness of the high porosity layer is, for example, 5 μm.

Thereafter, a non-porous single-crystal semiconductor layer 14 such as non-porous single-crystal silicon is formed on the porous layer 13. When the single crystal layer 14 is formed, for example, 100
Above 0 ° C., rearrangement of the pores inside the porous layer 13 occurs,
The characteristics of the accelerated etching are impaired. Therefore, before forming the single crystal layer 14, a protective film may be formed on the inner wall surface of the porous layer 13. Such a protective film can be formed by heat-treating the porous layer 13 at a temperature of about 300 ° C. to 600 ° C. in an oxidizing atmosphere.

Thereafter, the single crystal layer 14 is preferably formed by molecular beam epitaxial growth, plasma CVD, thermal CVD.
It is formed by a method, a photo CVD method, a bias sputtering method, a liquid phase growth method, or the like. Specifically, before the epitaxial growth, the porous layer 13 may be heat-treated in a hydrogen-containing reducing atmosphere. The hydrogen-containing reducing atmosphere is hydrogen 1
A 00% atmosphere or a mixed atmosphere of hydrogen and an inert gas. The heat treatment temperature is, for example, 800 ° C to 1200 ° C.

Next, as shown in FIG. 1E, an insulating layer 15 is formed on the non-porous single crystal layer 14 as necessary. Further, as shown in FIG. 1F, a second base 16 such as glass, quartz or a silicon support substrate is prepared, and an insulating layer 17 is formed on at least one surface of the second base 16 as necessary. .

When the insulating surfaces are bonded to each other as shown in the figure, it is preferable that at least one surface is exposed to nitrogen plasma or oxygen plasma to activate the surfaces.

Then, the first base 11 and the supporting substrate 16
Are bonded at room temperature via the insulating layers 15 and 17,
Bonding is performed by anodic bonding, pressing, heat treatment, or a combination thereof (FIG. 1 (g)). As a result, the support substrate 16 and the non-porous single crystal layer 14 are firmly bonded via the insulating layers 15 and 17. The insulating layer 1
The layers 5 and 17 may be formed on at least one of the non-porous single-crystal silicon layer 14 and the silicon support substrate 16 or may be laminated in three layers with the insulating layers 15 and 17 interposed therebetween.

Next, the bonded substrates are separated in the porous layer 13 and / or at the upper or lower interface (FIG. 1 (h)). The details of the separation method will be described later. On the support substrate 16 side, a composite member having a structure such as the residual porous body 13A / non-porous single crystal layer 14 / insulating layers 15, 17 / support substrate 16 is formed. Then, the residual porous body 13A remaining on the separation surface is selectively removed.

Hydrofluoric acid, a mixed solution obtained by adding at least one of alcohol and hydrogen peroxide to hydrofluoric acid, or buffered hydrofluoric acid or at least one of alcohol and hydrogen peroxide to buffered hydrofluoric acid Using at least one of the added mixed liquids, only the residual porous body 13A is subjected to electroless wet chemical etching to leave the single-crystal layer 14 thinned on the insulating layers 15, 17 and the supporting substrate 16.

As described above, only the porous body can be selectively removed by etching due to the huge surface area of the porous body. However, when a crack is generated at the interface between the porous layer 13 and the semiconductor layer 14 and the residual porous body 13A hardly exists, the above-mentioned etching step becomes unnecessary. When the porous layer is cracked and separated and the porous body 13 remains on the separation surface, it is necessary to remove the porous body.

The first substrate after separation can be used as a substrate on which the epitaxial growth layer 12 has already been formed by flattening and smoothing the surface roughness after separation. Methods for smoothing the surface roughness after separation include polishing and hydrogen annealing, but the method using hydrogen annealing can reduce the reduction of the substrate and can increase the number of times per epitaxial silicon layer deposition. This is preferable because the step of separating epitaxial silicon can be performed.

Hydrogen annealing is described in US Pat.
As proposed by the present inventors, it is proposed that the surface of an SOI substrate be smoothed by performing a heat treatment in an atmosphere containing hydrogen as described in the specification of Japanese Patent No. 9,387. Report that even if there is an uneven shape on the surface as compared with a commercially available polished silicon wafer, it has the effect of being improved to the same degree as a polished silicon wafer.

On the other hand, removal and smoothing of the residual porous body can be achieved in the same step by polishing. In this case, the porous layer 13 is removed by selective polishing using the non-porous single crystal layer 14 as a polishing stopper. FIG. 1 (l) shows the semiconductor member thus obtained. Insulating layers 15, 17
The thinned single crystal layer 14 is formed flat and uniformly on the support substrate 16 and is formed in a large area over the entire wafer. Thus, one semiconductor member having the SOI structure is obtained (first round). Further, the residual porous body 13
B / Remaining porous body 13B is selectively removed on the side of silicon single crystal substrate 11 having a structure like epitaxial growth layer 12/11.

Hydrofluoric acid, a mixed solution obtained by adding at least one of alcohol and hydrogen peroxide to hydrofluoric acid, or buffered hydrofluoric acid or at least one of alcohol and hydrogen peroxide to buffered hydrofluoric acid Using at least one of the added liquid mixtures, only the residual porous body 13B is removed by electroless wet chemical etching to obtain a structure of the epitaxial growth layer 12 / single crystal substrate 11 (FIG. 1 (i)).

The surface of the epitaxial growth layer 12 roughened by the removal of the residual porous body 13B is heat-treated in a reducing atmosphere containing hydrogen to flatten and smooth the surface of the epitaxial growth layer 12 (FIG. 1 (j)). The flattened epitaxial growth layer 12 and the first substrate 11 are shown in FIG.
It is used again as a substrate having the structure of (b) epitaxial growth layer 12 / single crystal substrate 11. Instead of the etching and the hydrogen annealing, the removal and smoothing of the residual porous body 13B may be performed by polishing.

Thereafter, the second cycle of steps (c) to (l) is performed to obtain a second semiconductor member having an SOI structure.

As described above, in the present embodiment, FIG.
As shown in FIG. 1B, since a relatively thick epitaxial growth layer 12 has been formed, the first substrate 11 having the flattened and smooth epitaxial growth layer 12 as shown in FIG. Figure 1 without application
The process can be shifted to the step (c). At this time, the thickness te of the residual epitaxial growth layer 12 is sufficiently larger than the thickness tps to be made porous next.

For example, in a commercially available batch-type epitaxial growth apparatus, each time one substrate is subjected to epitaxial growth, a substrate loading time, a temperature rising time, an effective epitaxial growth time, a temperature decreasing time, and a substrate unloading time are required.

According to this embodiment, at the time of the first round of epitaxial growth, the layer is formed to be thick including the portion of the epitaxial growth layer 12 consumed in the second and subsequent rounds.
The time for carrying in the substrate, the time for raising the temperature, the time for lowering the temperature, and the time for carrying out the substrate can be omitted for one time. If it is formed to be thick including the n-th round (n ≧ 3), it is possible to omit n-1 times.

Further, by forming the epitaxial growth layer 12 having a thickness corresponding to a plurality of separations at a time, it is possible to reduce the history of high temperature applied to the substrate when forming the epitaxial growth layer 12 and to reduce the number of steps. And cost can be reduced.

Further, as a method for separating both the silicon single crystal substrate 11 and the silicon support substrate 16 without breaking, the following method can be adopted.

One is a method of pulling in a direction crossing the bonding surface. This is to separate the silicon single crystal base 11 and the silicon support base 16 by applying an external force F1 to the end of the base 11, as shown in FIG. In this case, cracks extend from the end of the porous layer 13 toward the inside and are separated.

The second method is to apply a shearing stress in parallel to the bonding surface, more specifically, to move the respective substrates in directions parallel to the bonding surface in opposite directions, or in a circumferential direction. Then, the respective substrates are rotated in opposite directions. For this purpose, an external force F2 may be applied as shown in FIG.

A third method is to apply pressure in a direction intersecting the bonding surface. In this case, it can be considered that the direction in which the external force F1 shown in FIG. 2A is applied is reversed.

A fourth method is to apply energy F3 for peeling to the end of the porous layer 13 as shown in FIG. 2 (c). Specifically, it is peeled off from the end by inserting a sharp blade or spraying a high-pressure fluid. Further, the porous layer can be peeled off from the end surface by thermally oxidizing the end portion of the base to expand the volume of the porous layer. Furthermore, it is also possible to use a flexible substrate as the second base 16 and pull it to bend from the end face.

The separation method that can be used in the present invention is as follows:
U.S. Pat. No. 5,856,229; U.S. Pat.
854,123, JP-A-9-237884
JP-A-10-233352, JP-A-10-233352
No. 45840 describes this in detail. Alternatively, the separation may be performed by a method in which a porous layer functioning as a separation region is selectively etched and separated from the side surface of the bonded substrate.

FIG. 2D shows a method of injecting a liquid such as water or pure water or a gaseous fluid such as nitrogen, air, oxygen, hydrogen, carbon dioxide, or an inert gas into the end of the bonded substrate. NZ is a fluid ejection nozzle, and WJ is a fluid, which is separated into two by spraying the fluid onto a recess formed between the chamfered bases 11 and 16.

The epitaxial growth layer 12 is formed on the surface of the first substrate in advance to a thickness of at least n times (n ≧ 2) the thickness required for separation, and the separated first substrate is subjected to a surface smoothing step. The first substrate 1 again
1 can be used.

That is, assuming that the thickness of the epitaxial growth layer 12 formed on the first substrate 11 is te when the thickness from the surface of the isolation region in the epitaxial growth layer 12 is tps, the thickness of te is te ≧ ntps (n ≧ 2)
The thickness of one epitaxial growth layer 1
To reuse the first substrate 11 in the conventional process in order to enable the epitaxial silicon to be separated a plurality of times in the deposition of 1. 1. Formation of epitaxial growth layer 12 on the surface of first base 11 Separation 3. 3. Flatten the surface roughness of the first substrate 11 after separation. The epitaxial growth layer 12 is formed on the surface of the first base 11.
The process of forming 1. Formation of epitaxial growth layer 12 having a thickness of n separations on the surface of first base 11 Separation 3. This is a step of flattening the surface roughness of the first substrate 11 after the separation.

When a commercially available batch type epitaxial growth apparatus is used to form the epitaxial growth layer 12, for each formation of epitaxial silicon, the substrate is put into a chamber, and then the steps such as temperature increase, epitaxial growth, temperature decrease, etc. are performed. Is incorporated.

Therefore, by forming the epitaxial growth layer 12 having a thickness corresponding to a plurality of separations at a time,
This has the effect of reducing the high-temperature heat history applied to the substrate, reduces the number of steps, and enables cost reduction.

After two or more separation steps, the thickness te of the epitaxial growth layer 12 becomes te <ntpx (n ≧ n).
In the case of 1), the epitaxial growth layer 12 is formed on the first substrate 11 again so that the thickness of the epitaxial growth layer 12 becomes te ≧ nt (n ≧ 2).
It can be used as the first base 11 having the epitaxial growth layer 12 formed on the surface that can be subjected to a plurality of separation steps again.

In the conventional method, the structure of the porous layer 13 formed on the surface of the first substrate 11 is changed to the structure of the non-porous semiconductor layer crystal film formed on the porous layer 13. It is closely related to the number, and it is necessary to control the specific resistance of the first base 11 in order to control the structure of the porous layer 13.

However, by forming the epitaxial growth layer 12 on the surface of the first substrate 11,
Can be used as the epitaxial growth layer 12. The epitaxial growth layer 12 can control the specific resistance very strictly by controlling impurities during crystal growth,
This is a very effective means for controlling the porous structure.

Further, since the structure of the porous layer 13 is controlled by the specific resistance of the epitaxial growth layer 12 formed on the surface of the first base 11,
There is no need to select the type of the first base 11 that forms

That is, if the epitaxial growth layer 12 having an arbitrary specific resistance can be formed, the type of the first substrate serving as the base is not limited. Specifically, the p ⁺ high-quality substrate, the p ⁺ low-quality substrate, the p ⁻ low-quality substrate, the n ^{+
A +} low-quality substrate, an n ^- low-quality substrate, a p ^- high-quality substrate, and an n ⁺ high-quality substrate, and an n ^- high-quality substrate can be used as the first base 11 having the epitaxial growth layer 12 formed on the surface. That is to say.

Further, the structure of the porous layer 13 formed on the surface of the first base 11 depends on the number of stacking faults introduced into the non-porous semiconductor single crystal film formed on the porous layer 13, It is closely related to the structure of the high porosity layer used for separation. In a normal CZ substrate, the specific resistance in the ingot is 0.01 to
A variation of ± 50% is observed at 0.02 Ωcm.

When the specific resistance varies as described above, it becomes difficult to control the porous structure formed on the surface of the first substrate 11,
Variations in the stacking fault density of the epitaxial growth layer 12 and the structure of the high porosity layer used for separation lead to variations in the separation process, resulting in a lack of stability, making the control very difficult.

Therefore, by using the epitaxial growth layer 12 as the first substrate 11, the porous layer 13
Can be very strictly controlled by controlling impurities during crystal growth, so that the structure control of the porous layer 13 is very stable.

In order to control the structure of the porous layer of the epitaxial growth layer 12, it is preferable that the epitaxial growth layer 12 formed on the surface of the first substrate 11 be of p ⁺ or n ⁺ . In addition, swirls and COPs are present in commonly used CZ substrates. When a substrate having a COP is used for manufacturing an SOI wafer, when this COP is present in the SOI layer, a defect called an HF defect is formed.

Since there is no Si in the HF defect, SO
This is a fatal defect for an I substrate. The epitaxial growth layer 12 formed by CVD or the like is a commercially available epitaxial growth layer 12 having a resistivity in-plane variation of ± 5% and a wafer-to-wafer variation of ± 5%.
Since the specific resistance can be controlled with a very high accuracy of 7%, and there is no swirl due to the uneven concentration of impurities found in the CZ substrate, the porous layer 13 formed when the porous layer 13 is formed Can improve the uniformity of the thickness distribution.

Therefore, by using the epitaxial growth layer 12 as the first base 11, defects caused by swirl and COP existing in the CZ substrate can be eliminated. Defects can be greatly reduced.

However, the step of growing the epitaxial layer involves many steps and takes a long time, so that it has been a problem in terms of manufacturing tact time and manufacturing cost. Can be.

(Embodiment 2) Hereinafter, Embodiment 1 of the present invention will be described.
Another embodiment to which the method for manufacturing a semiconductor member according to the present invention is applied will be described. A method for manufacturing a semiconductor member according to the present embodiment will be described with reference to FIG. N-type 4 inch diameter first (100) single-crystal silicon substrate 31 having a thickness of 525 μm and a specific resistance of 0.01 Ω · cm to 100 Ω · cm
(FIG. 4A) An N-type single-crystal silicon layer 32 having a specific resistance of 0.01 Ω · cm is formed on 50 μmL PE (Liquid Phase E)
(pitaxy) method (FIG. 4B).

As a growth method, the single crystal silicon substrate 3
1 is immersed in a metal indium solvent at 900 ° C. dissolved in a supersaturated state, and then slowly cooled to form a single-crystal silicon layer 32 having a thickness of about 50 μm. The epitaxial silicon layer 32 on the surface of this substrate is anodized in an HF solution. Thus, a porous silicon layer 33 having a thickness of 9 μm is formed (FIG. 3C). The anodizing conditions are as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 11 (min) Thickness of porous silicon: 9 (μm) This substrate is oxidized in an oxygen atmosphere at 400 ° C. for 2 hours. Due to this oxidation, the inner wall of the hole of the porous silicon layer 33 is covered with the thermal oxide film. MBE (Mole) on the porous silicon layer 33
The single crystal silicon layer 34 is epitaxially grown to a thickness of 545 nm by a cular beam epitaxy method (FIG. 4D). The growth conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr (about 1.3 × 10 ⁻⁷ Pa) Growth rate: 0.1 nm / sec Temperature: 950 ° C. Growth rate: 0.3 μm / min Further, single crystal On the surface of the silicon layer 34, an SiO ₂ layer 35 of 100 nm is formed by thermal oxidation.
(E)). Separately, the surface of the fused quartz substrate 36 (FIG. 4 (f)) prepared as the second substrate and the surface of the SiO ₂ layer 35 are overlapped and brought into contact, and then heat-treated at 400 ° C. for 2 hours and bonded. (FIG. 4 (g)). Here, pre-processing such as N ₂ plasma processing is performed before overlapping.

A sufficient pressure is applied to the bonded wafer evenly in a direction perpendicular to the plane and further in the plane to break the porous silicon layer 33 to divide the wafer into two parts. Thus,
The porous silicon is exposed (FIG. 4 (h)). afterwards,
The porous silicon layer 33 is selectively etched while being stirred with a mixed solution (1: 5) of buffered hydrofluoric acid and a hydrogen peroxide solution having an H ₂ O ₂ concentration of 30 wt%. The single crystal silicon remains without being etched, and the porous silicon is selectively etched and completely removed using the single crystal silicon as a material for the etch stop (FIG. 4 (l)).

In this way, 0.5 μm
A single crystal silicon layer 34 having a thickness of m can be formed.

By using a substrate in which an epitaxial silicon layer 32 is formed on the surface of the first base 31, swirl-less and COP-free high quality in an HF defect test are used as compared with an SOI substrate manufactured using a conventional CZ substrate. An SOI substrate having a simple semiconductor layer can be obtained.

On the other hand, the porous silicon layer 33B remaining on the separated single crystal silicon substrate 31 is removed by similar etching (FIG. 4 (i)), and then the substrate is etched in a reducing atmosphere containing hydrogen. Heat treatment is performed to make the roughness flat (FIG. 4 (j)). The processing conditions are as follows.

Temperature: 1100 ° C. Time: 2 hours Source gas: H ₂ gas flow rate: 10 1 / min Gas pressure: Atmospheric pressure In the hydrogen annealing treatment, migration of surface atoms occurs in order to reduce the surface energy, so that the surface is roughened by selective etching. Can be flattened and smoothed. In the evaluation with an atomic force microscope, an average of 2
The roughness is 0.2 nm, which can be equal to or higher than that of a commercially available polished silicon substrate.

Using a substrate on which an epitaxial silicon layer 32 is stacked on a substrate on which a porous silicon layer 33 is to be formed, SO
In the case of fabricating an I-substrate, no swirl is observed even after heat treatment for flattening surface roughness due to etching in a reducing atmosphere containing hydrogen, and a good bonding state is obtained.

Using the thus obtained epitaxial silicon layer 32 and repeating the steps from the above-described porous layer forming step onward, an SOI having a high quality semiconductor layer is obtained.
Five substrates are obtained. Further, when the epitaxial silicon layer 32 has a thickness of 9 μm or less, single-crystal silicon is grown by using the LPE method, and the thickness of the epitaxial silicon layer 32 is returned to 50 μm again. By repeating the steps after the formation step, five more SOI substrates having a high-quality semiconductor layer can be obtained.

(Embodiment 3) A method of manufacturing a semiconductor member according to the present embodiment will be described with reference to FIG. 525 μm
Specific resistance 0.01Ω · cm to 100Ω · c with thickness of
m on a first (100) single-crystal silicon substrate 41 (FIG. 5 (a)) having a diameter of 4 inches and an N-type.
N-type single-crystal silicon from MBE (Mclecular Beam Epi
(taxy) method to form a layer 42 having a thickness of 20 μm (FIG. 5B). The growth conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr (1.3 × 10 ⁻⁷ Pa) Growth rate: 0.1 nm / sec Temperature: 950 ° C. The epitaxial silicon layer 42 on the surface of this substrate is HF
Anodizing is performed in the solution. Thus, the porous silicon layer 43 is formed (FIG. 5C). The anodizing conditions are as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1: 1 Time: 5 (min) Thickness of porous silicon: 5 (μm) This substrate is oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the hole of the porous silicon layer 43 is covered with the thermal oxide film. MOCVD on the porous silicon layer 43
Single crystal GaAs is epitaxially grown by a (Metal Organic Chemical Vapor Deposition) method to form a layer 44 having a thickness of 1 μm (FIG. 5D). The growth conditions are as follows.

Source gas: TMG / AsH ₃ / H ₂ gas pressure: 80 Torr (about 1.1 × 10 ⁴ Pa) Temperature: 700 ° C. Surface of second substrate 46 (FIG. 5 (f)) prepared separately and G
After overlapping and contacting the surface of the aAs layer 44, 90
Heat treatment is performed at 0 ° C. for 1 hour to perform bonding (FIG. 5).
(G)). By this heat treatment, both substrates are firmly bonded. A sufficient pressure is applied uniformly to the bonded wafer in the direction perpendicular to the surface and further in the surface to form a porous silicon layer 4.
3 is broken to divide the wafer into two (FIG. 5 (h)).

Then, after removing the oxide film on the inner wall of the residual porous silicon layer 43A with hydrofluoric acid, the porous silicon 43A is removed.
With ethylenediamine + pyrocatechol + water (17ml: 3
g: 8 ml) Etch at 110 ° C. The single-crystal GaAs layer 44 remains without being etched, and the porous silicon 43A is selectively etched using the single-crystal GaAs as a material for an etch stop, and is completely removed (FIG. 5 (l)).

The etching rate of the single crystal GaAs with respect to the etching solution is extremely low, and is considered to be a thickness reduction that can be ignored in practical use. That is, a single-crystal GaAs layer 44 having a thickness of 1 μm can be formed on the silicon substrate. The single crystal GaAs layer 44 does not change even by the selective etching of the porous silicon layer 43.

When a cross section is observed with a transmission electron microscope,
No new crystal defects have been introduced into the GaAs layer 44, and it can be confirmed that good crystallinity is maintained.
By using a silicon substrate with an oxide film as the support substrate 46, GaAs on an insulating film can be manufactured in a similar manner.

On the other hand, the porous silicon layer 43B remaining on the separated single crystal silicon substrate 41 is removed by the same etching (FIG. 5 (i)). Thereafter, the substrate is subjected to a heat treatment in a reducing atmosphere containing hydrogen to flatten the surface roughness due to the etching (FIG. 5 (j)). The processing conditions are as follows.

Temperature: 1100 ° C. Time: 1 hour Source gas: H ₂ gas flow rate: 10 l / min Gas pressure: Atmospheric pressure The mean square roughness in a 50 μm square region in the evaluation with an atomic force microscope was 0.2 nm. Thus, it can be made equal to or more than a polished silicon substrate which is usually commercially available.

By repeating the steps from the above-described porous layer forming step onward using the thus obtained epitaxial silicon layer 42, three compound semiconductor On Insulator substrates having a high-quality GaAs semiconductor layer can be obtained.

Further, when the thickness of the epitaxial silicon layer 42 becomes 5 μm or less, the MBE (Mole
The thickness of the epitaxial silicon layer 42 is returned to 20 μm by a cular beam epitaxy method, and the above-described steps after the porous layer forming step are repeated to further three compound semiconductor On Insulator substrates having a high-quality semiconductor layer. Can be obtained.

[0104]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] Referring to FIG. 1 again, a method for manufacturing a semiconductor member of this embodiment will be described. As a first substrate, a specific resistance of 0.01 Ω · cm having a thickness of 725 μm
P type 8-inch diameter (100) single crystal silicon substrate 1
1 (FIG. 1A), a P-type single crystal silicon layer having a specific resistance of 0.01 Ω · cm
The epitaxial growth layer 12 was grown by VD (Chemical Vapor Deposition) to a thickness of 30 μm (FIG. 1B).

The growth conditions were as follows.

Source gas: SiHCl ₃ / H ₂ dopant: B ₂ H ₆ Gas pressure: 760 Torr (about 1.0 × 10 ⁵ Pa) Temperature: 1080 ° C. Growth rate: 2 μm / min Epitaxially grown layer 12 on the surface of this substrate Was anodized in an HF solution. Thus, a porous silicon layer 13 having a thickness of, for example, 11 μm was formed on the surface of the epitaxial growth layer 12 (FIG. 1C). The anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 11 minutes Porous thickness: 11 μm Porosity: 20% This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. By this oxidation, the porous silicon layer (porous semiconductor layer) 13
The inner wall of the hole was covered with a thermal oxide film. Then, after immersing in a HF solution having a HF concentration of 1.2 wt% for 30 seconds to remove the thermal oxide film on the surface of the porous semiconductor layer, the porous semiconductor layer is thoroughly washed with water, dried, placed in an epitaxial apparatus, and placed in an hydrogen atmosphere. After the temperature is raised, single-crystal silicon is epitaxially grown on the porous silicon layer 13 by a CVD method to a thickness of, for example, 10 μm.
A 45 nm single crystal silicon layer 14 was formed (FIG. 1).
(D)). The growth conditions were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.1 / 25 l / min Gas pressure: 760 Torr (about 1.0 × 10 ⁵ Pa) Temperature: 950 ° C. Growth rate: 0.2 μm / min Further, an SiO ₂ layer 15 having a thickness of 100 nm was formed as an insulating layer on the surface of the single-crystal silicon layer 14 by thermal oxidation (FIG. 1E). A silicon substrate 16 (FIG. 1) on which a separately prepared 500 nm SiO ₂ layer (insulating layer) 17 was formed.
The (f)) side of the SiO ₂ layer 17 and the surface of the SiO ₂ layer 15 were overlapped and brought into contact with each other, and then heat-treated at 1100 ° C. for 2 hours to perform bonding (FIG. 1 (g)).

The porous silicon layer 13 was broken by applying a sufficient tensile force in the direction perpendicular to the surface of the bonded substrate, and the substrate was divided into two parts to expose the porous silicon (FIG. 1 (h)). ).

[0111] Specifically, both sides of the bonded substrate are pressed.
The plates are glued together with glue and the plates are pulled together.
After arranging on a jig that moves in the separating direction,
Pulled apart. After that, the porous silicon layer 13 is
Hydrofluoric acid with a concentration of 49 wt% and H _TwoO_TwoConcentration 30wt% peroxide
Selective etching while stirring with a mixture of hydrogen water (1: 5)
I did.

The single-crystal silicon remains without being etched, and the porous silicon is etched and completely removed using the single-crystal silicon as an etch stop material to obtain one SOI substrate (FIG. 1 (l)). .

The etching rate of the non-porous silicon with respect to the etching solution is extremely low, the selectivity with respect to the etching rate of the porous layer reaches 10 ⁵ or more, and the etching amount (number) 1
(About 0 nm) was a practically negligible decrease in film thickness. That is, the single-crystal silicon layer 14 having a thickness of 1 μm was formed on the SiO ₂ layers 15 and 17. The single crystal silicon layer 14 did not change even by the selective etching of the porous silicon.

As a result of observation of a cross section with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer, and good crystallinity was maintained. After immersing this substrate in a high-concentration HF solution having a HF concentration of, for example, 40 wt% to 49 wt% for 15 minutes, the entire surface of the substrate was checked with an optical microscope. And very few.

That is, by using a substrate in which the epitaxial growth layer 12 is formed on the surface of the single crystal silicon substrate 11, the S fabricated by using the conventional CZ substrate in the HF defect test.
An SOI substrate having a COP-free high-quality semiconductor layer as compared with the OI substrate was obtained. The single-crystal silicon layer 1
The same result can be obtained by bonding without forming the oxide film 15 on the surface of No. 4. Further, the same result can be obtained even if the bonding is performed without forming the oxide film 17 on the surface of the Si substrate 16.

On the other hand, the porous silicon layer 13 remaining on the single crystal silicon substrate 11 separated by the porous silicon layer 13
Is removed by the same etching (FIG. 1).
(I)) The substrate was heat-treated in a reducing atmosphere containing hydrogen to flatten the surface roughness due to etching (FIG. 1 (j)). The heat treatment conditions were as follows.

Temperature: 1100 ° C. Time: 1 hour Source gas: H ₂ gas flow rate: 10 1 / min Gas pressure: 760 Torr (approximately 1.0 × 10 ⁵ Pa) In the hydrogen annealing treatment, surface atoms are reduced to reduce surface energy. Since migration occurs, surface roughness due to selective etching can be flattened and smoothed. In the evaluation with an atomic force microscope, the mean square roughness in a 50 μm square region was 0.2 nm, which could be equal to or more than that of a commercially available polished silicon substrate.

The remaining thickness thus obtained is about 19 μm
By repeating the steps from the step of forming the porous silicon layer 13 using the epitaxially grown layer 12, another two SOI substrates having a high-quality semiconductor layer were obtained.

The epitaxial growth layer 12 has a thickness of about 8
μm, single-crystal silicon is grown using the CVD method, and the thickness of the epitaxial growth layer 12 is reduced to 3 μm.
The third SOI substrate having a high-quality semiconductor layer was obtained by setting the thickness to 0 μm and repeating the steps from the above-described porous layer forming step onward. Further, the above-described porous formation step and subsequent steps were repeated to obtain a fourth SOI substrate.

Embodiment 2 Referring again to FIG. 1, it is a diagram showing a method of manufacturing a semiconductor member of the present embodiment. 625 μm
A P-type 6-inch diameter (100) single-crystal silicon substrate 11 having a specific resistance of 0.01 Ω · cm (FIG. 1)
(A)) is prepared and placed in an epitaxial growth apparatus,
The temperature was raised in hydrogen, and P-type single crystal silicon having a specific resistance of 0.05 Ω · cm was grown on the silicon single crystal substrate 11 by the CVD method to obtain an epitaxially grown layer 12 having a thickness of 40 μm (FIG. 1B). ). The growth conditions were as follows.

Source gas: SiHCl ₃ / H ₂ dopant: B ₂ H ₆ Gas pressure: 760 Torr (approximately 1.0 × 10 ⁵ Pa) Temperature: 1080 ° C. Growth rate: 2 μm / min The surface of the epitaxial silicon of this substrate is HF Anodization was performed in the solution. Thus, for example, a thickness of 8
A μm porous silicon layer 13 was formed (FIG. 1).
(C)). The anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 10 (min) Thickness of porous silicon: 8 (μm) This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the hole of the porous silicon layer 13 was covered with the thermal oxide film. Thereafter, the porous layer is immersed in a 1.0% by weight HF solution for 45 seconds to remove the thermal oxide film on the surface of the porous layer, washed well, dried well, and placed in an epitaxial apparatus to raise the temperature in hydrogen. Then, single crystal silicon was epitaxially grown on the porous silicon layer 13 by a CVD method to form a single crystal silicon layer 14 having a thickness of 1045 nm (FIG. 1D). The growth conditions were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 80 Torr (about 1.1 × 10 ⁴ Pa) Temperature: 950 ° C. Growth rate: 0.3 μm / min Further, the surface of the single crystal silicon layer 14 is
A 00 nm SiO ₂ layer 15 was formed (FIG. 1E).
Silicon substrate 16 formed with the SiO ₂ layer 17 of 500nm separately prepared SiO ₂ layer 17 side and S in (FIG. 1 (f))
After overlapping and contacting the surface of the iO ₂ layer 15, 9
Heat treatment was performed at 00 ° C. for 2 hours, and bonding was performed (FIG. 1 (g)). Here, if the bonding surfaces are subjected to a pretreatment such as N ₂ plasma treatment before they are superposed, the bonding strength is further increased.

As shown in FIG. 2D, the wafers bonded to each other are set upright, and the water jet device placed above the gap (recess) formed by beveling the two wafers is placed above the water jet device. 2000k from 15mm nozzle
High-pressure pure water was sprayed at a pressure of gf / cm ² from a direction parallel to the bonding interface (surface) of the bonded wafer.
At that time, the nozzle was scanned in a direction in which high-pressure pure water moved along a gap formed by beveling.

As a result, the wafer was divided into two in the porous silicon layer 13 formed by anodization (FIG. 1 (h)). At this time, the silicon single crystal substrate 11
A part of the SiO ₂ layer 15, the single crystal silicon layer 14, and the porous silicon layer 13 formed on the surface were transferred to the silicon substrate 16 where the bonding was performed. Only the porous silicon layer 13 remained on the surface of the epitaxial growth layer 12 on the single crystal silicon substrate 11.

Thereafter, the porous silicon layer 13 was selectively etched while being stirred with a mixed solution (1: 5) of hydrofluoric acid having a HF concentration of 49 wt% and hydrogen peroxide having a H ₂ O ₂ concentration of 30 wt%. The single-crystal silicon remained without being etched, and the porous silicon was selectively etched and completely removed using the single-crystal silicon as a material for the etch stop (FIG. 1 (l)).

That is, 1 μm is formed on the SiO ₂ layers 15 and 17.
The single crystal silicon layer 14 having a thickness of m was formed.
The single crystal silicon layer 14 did not change even by the selective etching of the porous silicon. As a result of cross-sectional observation with a transmission electron microscope, no new crystal defects were introduced into the silicon layer, and it was confirmed that good crystallinity was maintained. After immersing this substrate in a high-concentration HF solution for 15 minutes, the entire surface of the substrate was confirmed by an optical microscope. As a result, there were very few holes in the buried oxide film (BOX) due to HF.

That is, by using a substrate on which the epitaxial growth layer 12 is formed on the surface of the single crystal silicon substrate 11, it is swirlless compared to a SOI substrate manufactured using a conventional CZ substrate, and is free of COP in the HF defect test. An SOI substrate having a high-quality semiconductor layer was obtained.

On the other hand, the porous silicon layer 13 remaining on the single crystal silicon substrate 11 separated by the porous silicon layer 13 was removed by the same etching (FIG. 1).
(I)) Thereafter, the surface roughened by etching was polished and removed by 5 μm to flatten the surface roughness (FIG. 1 (j)). By this flattening, the substrate surface was able to have the same surface flatness as a commercially available substrate.

Using the remaining epitaxially grown layer 12 having a thickness of about 32 μm obtained as described above, a second SOI substrate having a high-quality semiconductor layer is obtained by repeating the steps from the above-described step of forming the porous layer. Was done. Further, similarly, a third SOI substrate was obtained using the epitaxial growth layer 12 having a thickness of about 24 μm. Then, a fourth SOI substrate was obtained using the epitaxial growth layer 12 having a thickness of 16 μm. Then, a fifth SOI substrate was obtained using the epitaxial growth layer 12 having a thickness of 8 μm.

The polished epitaxial silicon layer has a thickness of 8 μm.
When the thickness becomes less than m, single-crystal silicon corresponding to the used epitaxial growth layer 12 is formed by CVD, and the thickness of the epitaxial silicon layer is returned to 40 μm again. By repeating the steps after the silicon layer forming step, five more SOI substrates having high-quality semiconductor layers can be manufactured.

[Embodiment 3] A method for manufacturing a semiconductor member of this embodiment will be described with reference to FIG. A P-type first (100) single-crystal silicon substrate 51 having a thickness of 625 μm and a specific resistance of 0.01 Ω · cm and having a diameter of 6 inches (FIG. 3)
(A)) P-type single-crystal silicon having a specific resistance of 0.01 Ω · cm was grown thereon by CVD to form an epitaxial silicon layer 52 having a thickness of, for example, 30 μm (FIG. 3).
(B)). The growth conditions were as follows.

Source gas: SiHCl_Three/ H_Two  Dopant: B_TwoH₆ Gas pressure: 760 Torr (about 1.0 × 10^FivePa) Temperature: 1080 ° C. Growth rate: 2 μm / min Surface of the epitaxial silicon layer 52 on the surface of this substrate
Is anodized in the HF solution under the first condition,
Thereafter, anodization was performed under the second condition. Thus,
A number of porous silicon layers 53 were formed (FIG. 3C).
The anodizing conditions were as follows. (First condition) Current density: 7 (mA · cm)^-2) Anodizing solution: HF: H_TwoO: C_TwoH_FiveOH = 1: 1: 1 Time: 5 (min) Thickness of the porous silicon layer 53 ′: 4.5 (μm) Porosity: 15 (%) (Second condition) Current density: 30 (mA · cm)^-2) Anodizing solution: HF: H_TwoO: C_TwoH_FiveOH = 1: 1: 1 Time: 10 (sec) Thickness of porous silicon layer 53 ″: 0.2 (μm) Porosity: 40 (%) By forming porous silicon layer 53 into a two-layer structure, Destination
Surface porous silicon layer 5 anodized at low current
3 'to form a high quality epitaxial silicon layer
And later anodized at a high current
Porous silicon layer is used to form an effective separation layer
Each was formed. Therefore, low current
The thickness of the porous silicon layer 53 'is not limited to this,
It can be used from several hundred μm to about 0.1 μm. Ma
After the formation of the second porous silicon layer 53 ″, the third and subsequent layers are formed.
A descent may be formed.

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. The inner walls of the pores of the porous silicon formed on the surface of the epitaxial silicon by this oxidation were covered with the thermal oxide film. After that, 4%
After immersion for 5 seconds, the substrate was thoroughly washed with water, dried thoroughly, set in an epitaxial apparatus, heated in hydrogen, and a single-crystal silicon layer 54 having a thickness of, for example, 1045 nm was epitaxially grown on the porous silicon by CVD (FIG. 3). (D)). The growth conditions were as follows.

Source gas: SiH_TwoCl_Two/ H_Two Gas flow rate: 0.5 / 180 l / min Gas pressure: 80 Torr (about 1.1 × 10^FourPa) Temperature: 950 ° C. Growth rate: 0.3 μm / min.
100 nm SiO by oxidation_TwoA layer 55 was formed (see FIG.
3 (e)). Separately prepared 100nm SiO _TwoLayer 57
Of silicon substrate 56 (FIG. 3 (f)) on which_Two
Layer 57 side and SiO_TwoSuperimpose on the surface of layer 55 and make contact
After that, a heat treatment is performed at 900 ° C. for 2 hours to form a second base.
56 was bonded (FIG. 3 (g)).

As shown in FIG. 2D, the bonded wafers are set upright, and the gap formed by beveling the two wafers is inserted into the gap formed by the 0.15 mm nozzle of the water jet device placed above the gap. 2000kgf / cm
^At a pressure of ² , high-pressure pure water was sprayed from a direction parallel to the bonding interface (surface) of the bonded wafer. At that time, the nozzle was scanned in a direction in which high-pressure pure water moved along a gap formed by beveling.

As a result, a crack was generated near the interface of the porous silicon layer 53 ″ formed by the high current, and the wafer was divided into two parts (FIG. 3 (h)). As a result, the wafer was formed on the original substrate surface. The SiO ₂ layer 55, the epitaxial silicon layer 54, and a part of the porous silicon layers 53 ′ and 53 ″ were transferred to the side of the second substrate 56 where they were bonded. Only the porous silicon layer 53 ″ remained on the surface of the first substrate 51.

Thereafter, the porous silicon layers 53 ', 53 "
Was selectively etched while stirring with a mixed solution (1: 5) of hydrofluoric acid having an HF concentration of 49 wt% and hydrogen peroxide aqueous solution having an H ₂ O ₂ concentration of 30 wt%. The single-crystal silicon remained without being etched, and the porous silicon was selectively etched and completely removed using the single-crystal silicon as a material for the etch stop (FIG. 3 (l)).

That is, a single-crystal silicon layer having a thickness of 1 μm was formed on the SiO ₂ layer. The single crystal silicon layer 54 did not change even by the selective etching of the porous silicon. As a result of cross-sectional observation with a transmission electron microscope, no new crystal defects were introduced into the silicon layer, and it was confirmed that good crystallinity was maintained.
After immersing this substrate in a high-concentration HF solution for 15 minutes, the entire surface of the substrate was confirmed by an optical microscope. As a result, there were very few holes in the buried oxide film (BOX) due to HF.

That is, by using a substrate in which an epitaxial silicon layer 52 is formed on the surface of a single crystal silicon substrate 51, it is swirlless compared to an SOI substrate manufactured using a conventional CZ substrate, and a COP-free film is obtained by an HF defect test. An SOI substrate having a high quality semiconductor layer was obtained.

On the other hand, the porous silicon layer 53 ″ remaining on the single crystal silicon substrate 51 separated by the porous silicon layer 53 ″ is removed by the same etching (FIG. 3).
(I)) Thereafter, the substrate was heat-treated in a reducing atmosphere containing hydrogen to flatten the surface roughness due to etching (FIG. 3 (j)). The processing conditions were as follows.

Temperature: 1100 ° C. Time: 1 hour Source gas: H ₂ gas flow rate: 10 1 / min Gas pressure: 760 Torr (approximately 1.0 × 10 ⁵ Pa) In an area of 50 μm square in the evaluation with an atomic force microscope. Was 0.2 nm, which was equal to or higher than that of a commercially available polished silicon substrate.

However, when an SOI substrate was manufactured by stacking the epitaxial silicon layer 54 on the substrate on which the porous layer 53 was formed, heat treatment was performed in a reducing atmosphere containing hydrogen to flatten the surface roughness due to etching. Later, no swirl was observed, and a good bonded state was obtained.

Using the epitaxial silicon layer 52 thus obtained, the steps from the porous layer forming step onward were repeated five more times to obtain a total of six SOI substrates having high quality semiconductor layers.

When the thickness of the epitaxial silicon layer 52 becomes 5.2 μm or less, the thickness of the epitaxial silicon layer is returned to 30 μm again by using the CVD method, By repeating the steps from the above, six more S layers having a high-quality semiconductor layer
OI substrate fabrication can be obtained.

[Embodiment 4] A method of manufacturing a semiconductor member according to this embodiment will be described with reference to FIG. An N-type first (100) single-crystal silicon substrate 51 having a thickness of 525 μm and a specific resistance of 0.01 Ω · cm and a diameter of 4 inches (see FIG. 3)
(A)) An epitaxial silicon layer 52 having a thickness of 30 μm was obtained by growing on the N-type single crystal silicon layer CVD method having a specific resistance of 0.01 Ω · cm (FIG. 7B). The growth conditions were as follows.

Source gas: SiHCl ₃ / H ₂ dopant: PH ₃ Gas pressure: 760 Torr (approximately 1.0 × 10 ⁵ Pa) Temperature: 1080 ° C. Growth rate: 2 μm / min The surface of the epitaxial silicon layer of this substrate is HF solution In this, anodization was performed under the first condition, and then anodization was performed under the second condition. Thus, the porous silicon layer 53
Was formed (FIG. 3C). The anodizing conditions were as follows. (First condition) Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 5 (min) For porous silicon layer 53 ′ Thickness: 4.5 (μm) Porosity: 15% (Second condition) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 10 (seconds) Thickness of the porous silicon layer 53 ″: 0.2 (μm) Porosity: 40 (%) This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the hole of the porous silicon layer 53 was covered with the thermal oxide film. After that, the porous oxide layer was immersed in a 1.0% by weight HF solution for 45 seconds to remove the thermal oxide film on the surface of the porous layer, washed well with water, dried well, and placed in an epitaxial device to place the porous layer on the porous silicon layer 53. 104 by CVD
A single-crystal silicon layer 54 having a thickness of 5 nm was epitaxially grown (FIG. 3D). The growth conditions were as follows.

Source gas: SiH_TwoCl_Two/ H_Two Gas flow rate: 0.5 / 180 l / min Gas pressure: 80 Torr (about 1.1 × 10^FourPa) Temperature: 950 ° C. Growth rate: 0.3 μm / min.
100 nm SiO by oxidation_TwoA layer 55 was formed (see FIG.
3 (e)). 500nm SiO prepared separately _TwoLayer 57
Of silicon substrate 56 (FIG. 3 (f)) on which_Two
Layer 57 side and SiO_TwoOverlap and contact the surface of layer 65
After that, a heat treatment is performed at 900 ° C. for 2 hours to form a second base.
No. 66 was bonded (FIG. 3 (g)).

The wafer bonded as shown in FIG. 2D is set upright, and the gap between the beveling of both wafers is set to 2000 kgf from the 0.15 mm nozzle of the water jet device placed above it. High-pressure pure water at a pressure of / cm ² was sprayed from a direction parallel to the bonding interface (surface) of the bonded wafer. At that time, the nozzle was scanned in a direction in which high-pressure pure water moved along a gap formed by beveling.

As a result, a crack was generated along the interface of the porous silicon layer 53 ″ formed by the high current, and the wafer was divided into two parts (FIG. 3 (h)). The formed SiO ₂ layer 55, epitaxial silicon layer 54 and porous silicon layer 53 ′,
A part of 53 ″ was transferred to the side of the second substrate 56 to which it was bonded. The porous silicon layer 5 was formed on the surface of the first substrate 51.
Only 3 "remained.

Thereafter, the porous silicon layers 53 ', 53 "
HF concentration of 49 wt% hydrofluoric acid and H _TwoO_TwoThe concentration is 30wt
While stirring with a mixed solution (1: 5) with aqueous hydrogen peroxide
Selective etching. Single crystal silicon is etched
And use single crystal silicon as the etch stop material
As a result, the porous silicon is selectively etched and completely removed.
(FIG. 3 (l)).

That is, 1 μm is formed on the SiO ₂ layers 55 and 57.
A single crystal silicon layer 54 having a thickness of m was formed.

The single crystal silicon layer did not change even by the selective etching of the porous silicon. As a result of cross-sectional observation with a transmission electron microscope, no new crystal defects were introduced into the silicon layer, and it was confirmed that good crystallinity was maintained. After immersing this substrate in a high-concentration HF solution for 15 minutes, the entire surface of the substrate was confirmed with an optical microscope.
As a result, there were very few holes with holes in the buried oxide film (BOX).

That is, by using a substrate in which an epitaxial silicon layer 52 is formed on the surface of a polycrystalline silicon substrate 51, an SOI fabricated using a conventional CZ substrate is used.
An SOI substrate having a high-quality COP-free semiconductor layer was obtained in the HF defect test without swirl compared to the substrate.

On the other hand, after the porous silicon layer 53 ″ remaining on the single crystal silicon substrate 51 is removed by the same etching (FIG. 3 (i)), the substrate is roughened by etching in a reducing atmosphere containing hydrogen. (FIG. 3 (j)) The heat treatment was carried out in order to make the surface flat.

Temperature: 1100 ° C. Time: 1 hour Source gas: H ₂ gas flow rate: 10 1 / min Gas pressure: Atmospheric pressure In the hydrogen annealing treatment, migration of surface atoms occurs in order to reduce surface energy, so surface roughness due to selective etching Could be flattened and smoothed. In the evaluation with an atomic force microscope, an average of 2
The roughness was 0.2 nm, which was equal to or higher than that of a commercially available polished silicon substrate.

By using the epitaxial silicon layer 52 thus obtained and repeating the steps after the above-described porous layer forming step, an SOI having a high quality semiconductor layer is obtained.
Six substrates were obtained.

After that, when the thickness of the epitaxial silicon layer 52 becomes 5 μm or less, the thickness of the epitaxial silicon layer 52 is returned to 30 μm again by using the CVD method, and the steps after the above-described porous layer forming step are performed. Is repeated, so that six more SOs having a high-quality semiconductor layer
An I substrate was obtained.

(Comparative Example) An SOI substrate was manufactured in the same manner as in Example 1 except that the epitaxial growth step in FIG. 1B was omitted. That is, a porous silicon layer 13 is formed on the surface of a normally available CZ substrate without epitaxial growth, and a single-crystal silicon layer 14 is formed on the porous silicon layer 13. The substrate 16 is bonded to the substrate 16, the base formed by bonding is separated in the porous silicon layer 13, the porous silicon layer 13 disposed on the separated single crystal silicon substrate 11 is removed, and hydrogen is contained. When heat treatment was performed in a reducing atmosphere to flatten the surface roughness due to etching, swirl was observed on the surface by differential interference with an optical microscope.

In the case where an SOI substrate was manufactured using this substrate again as the single crystal silicon substrate 11, the bonding failure due to the swirl portion occurred very much in the bonding step.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor member according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a separation method used in the present invention.

FIG. 3 is a view showing another method of manufacturing a semiconductor member according to the present invention.

FIG. 4 is a view showing a method for manufacturing still another semiconductor member of the present invention.

FIG. 5 is a view showing another method for manufacturing a semiconductor member of the present invention.

FIG. 6 is a view showing a conventional method for manufacturing a semiconductor member.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 1st base | substrate 12 Epitaxial growth layer 13 Porous layer 14 Single crystal layer 15 Insulating layer 16 2nd base | substrate 17 Insulating layer

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takao Yonehara 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term (reference) in Canon Inc. 4G077 AA03 BA04 DB05 ED06 FB06 FF07 FG13 HA06 HA12 TB02 TC19 5F045 AA03 AA04 AA08 AA11 AA19 AB02 AB05 AB06 AB10 AB12 AB14 AB32 AC01 AC05 AC08 AD11 AD13 AD14 AE03 AE25 AF02 AF03 AF04 AF07 AF16 AF19 DA52 EB15 GH02 GH08 HA14 HA16 5F052 AA11 CA10 DA01 DA05 DB01 DB03 DB06 DB07 DB09 GC03 JA04 KB04

Claims (27)

[Claims] A step of forming a porous semiconductor layer on at least one surface of a first base; a step of forming a non-porous single-crystal semiconductor layer on the porous semiconductor layer;
A method of manufacturing a semiconductor member, comprising: a step of bonding the non-porous single-crystal semiconductor layer of the base and the second base; and a step of separating the bonded base by the porous semiconductor layer. In the above, before the step of forming the porous semiconductor layer, an epitaxial growth layer is formed on the one surface of the first base to a thickness of at least n times (n ≧ 2) the thickness of the porous semiconductor layer. A method for manufacturing a semiconductor member, comprising: a step of forming a porous semiconductor layer on the epitaxially grown layer after separation. 2. The method according to claim 1, wherein the first base and the second base are bonded together with an insulating layer interposed therebetween. 3. The step of removing at least the porous semiconductor layer from the separated first substrate, and the step of removing the surface of the first substrate from which the porous semiconductor layer has been removed in a reducing atmosphere containing hydrogen. 3. The method of manufacturing a semiconductor member according to claim 1, further comprising a step of performing a heat treatment to smooth the semiconductor member. 4. The method according to claim 3, wherein the smoothing is performed by polishing. 5. The method of claim 1, wherein the thickness of the epitaxial growth layer is t
e, when the thickness of the porous semiconductor layer is tps, and te ≦ n × tps (n ≧ 1), the epitaxial growth layer is subjected to epitaxial growth, and te ≧ n × tps (n ≧ 2) The method of manufacturing a semiconductor member according to claim 1, wherein: 6. The etching of each of the porous semiconductor layers on the first substrate side and the second substrate side by adding hydrofluoric acid or at least one of an alcohol and a hydrogen peroxide solution to hydrofluoric acid. Solution or buffered hydrofluoric acid or an etchant obtained by adding at least one of alcohol and hydrogen peroxide to buffered hydrofluoric acid,
The method for manufacturing a semiconductor member according to claim 1, wherein the semiconductor member is removed by infiltration. 7. The division of the first base and the second base may be performed by applying pressure in a direction perpendicular to a bonding surface, and by vertically applying a surface to each of the first base and the second base. Pulling or applying shear stress in any direction,
The method for manufacturing a semiconductor member according to claim 1, wherein the method is performed by at least one or more methods. 8. The method according to claim 6, wherein each of the porous semiconductor layers on the first substrate side and the second substrate side is selectively etched with the etching solution. A method for manufacturing a semiconductor member. 9. The method according to claim 1, wherein the removal of the porous semiconductor layer is performed by polishing using the non-porous single-crystal semiconductor layer as a stopper. . 10. The method according to claim 1, wherein the step of bonding the first substrate and the second substrate is performed by a method selected from anodic bonding, pressing, heat treatment, or a combination thereof. A method for manufacturing a semiconductor member according to any one of claims 1 to 5. 11. The method according to claim 1, wherein the step of forming the porous semiconductor layer is performed by anodization.
6. The method for manufacturing a semiconductor member according to any one of the above items 5. 12. The method according to claim 1, wherein the porous semiconductor layer includes a plurality of layers having different porosity. 13. The semiconductor according to claim 12, wherein the porous semiconductor layer is formed in the order of at least a low porosity layer and a high porosity layer from the main surface side of the second substrate. How to make the member. 14. The method according to claim 13, wherein the porosity of the low porosity layer is less than 30%. 15. The method according to claim 13, wherein the porosity of the high porosity layer is 30% or more. 16. The method according to claim 13, wherein the thickness of the high porosity layer is 5 μm or less. 17. The method for separating the porous semiconductor layer, comprising: attaching a flexible film to the surface of the non-porous semiconductor layer;
6. The method according to claim 1, wherein the film is peeled off.
13. The method for producing a semiconductor member according to the above item. 18. The method according to claim 1, wherein the separating step includes inserting a wedge into an end of the bonded substrate.
The method for manufacturing a semiconductor member according to any one of the above. 19. The semiconductor according to claim 1, wherein in the separating step, an external force is applied to the bonded substrate in a direction perpendicular to the surface to pull or press the bonded substrate. How to make the member. 20. The method according to claim 1, wherein in the separating step, the porous semiconductor layer is oxidized from an end of the bonded substrate, and a pseudo wedge is inserted by expansion of the porous semiconductor layer. A manufacturing method of the semiconductor member according to the above. 21. The method for manufacturing a semiconductor member according to claim 1, wherein in the separating step, a fluid is jetted to an end of the bonded substrate. 22. The method according to claim 21, wherein the fluid is a liquid. 23. The method according to claim 22, wherein the liquid is water or pure water. 24. The method according to claim 21, wherein the fluid is a gas. 25. The method according to claim 24, wherein the gas is one of nitrogen, air, oxygen, hydrogen, carbon dioxide, and an inert gas. 26. A step of forming an epitaxially grown layer having a thickness of te on the surface of the first substrate; and forming a porous layer having a thickness of tps on the surface of the epitaxially grown layer so as not to exceed half the thickness of te. Forming a non-porous layer on the porous layer; separating the non-porous layer from the first substrate; forming a porous layer on the surface of the epitaxially grown layer after the separation. Forming a layer. 27. After the step of separating the non-porous layer from the first substrate, a step of smoothing the surface of the epitaxial growth layer, and forming the porous layer on the smoothed surface of the epitaxial growth layer. 27. The semiconductor according to claim 26, further comprising: a step of forming a non-porous layer on the porous layer; and a step of separating the non-porous layer from the first base. How to make the member.